Hardware Platform Design Research Articles

A Methodical Approach to Hardware Platform Design for sEMG Recording and Classification Hand Gesture Recognition using sEMG

A Methodical Approach to Hardware Platform Design for sEMG Recording and Classification Hand Gesture Recognition using sEMG

Switching-mode audio amplifier based on a ΔΣ A/D converter

The article describes the design and implementation of a modular hardware platform intended for testing and measuring various configurations of switching-mode audio amplifiers based on sigma-delta modulation. Two single-channel power amplifier modules were designed and manufactured, along with a stereophonic module serving as the basic source of modulated signals. Additionally, measurements were conducted on the fundamental parameters of the completed amplifier, such as harmonic distortion level, dynamic range, and output power. The developed platform serves as a foundation for modifications and further advancement in the technology of building switching-mode audio amplifiers.

A Medium-Voltage Current Source Inverter for Synchronous Electrostatic Drives

Macro scale synchronous electrostatic machines (SEMs) require medium voltage (5kV) and high fundamental frequencies (high pole number ~ 96) to be competitive with traditional electromagnetic machines. This paper focuses on the design, modeling, and characterization of a medium voltage current source inverter hardware platform to meet the low current and high frequency requirements of SEMs. The inverter stage utilizes JFET super cascodes for the medium voltage switches. A full-bridge front end regulates the necessary dc-link current and provides some of the voltage gain from the low voltage dc input. A sensitivity analyses shows that the system losses have a quadratic dependence on output voltage and a linear dependence on switching frequency and dc-link current. Minimal dependence on output power and fundamental frequency were measured. Averaged modeling shows a right-half-plane pole exists for the dc-link control. Two methods for stabilizing the machine drive were proposed and validated. Active damping via virtual resistance on the dc link was used to shift the pole to the left half plane. The second method utilizes q-axis voltage decoupling to remove the voltage disturbance of the inverter controller on the dc-link current. The impacts on system stability and disturbance rejection were measured and correlate with modeling.

FRI Sampling of Parametric Signals With Non-Ideal Sinc Kernel

Recent developed finite rate of innovation (FRI) theory provides an efficient way for sub-Nyquist sampling of wideband parametric signals in the fields of radar and communication. However, the existing hardware schemes of FRI sampling systems have not considered the non-ideal effects of physical components, which lead to low accuracy in the signal reconstruction process. In this brief, we propose a FRI sampling system for parametric signals with non-ideal sinc kernel, which significantly improves the reconstruction performance under non-ideal hardware environment. The proposed system consists of two parallel sampling channels. The first channel samples the parametric signal at a low speed after filtered with a LPF, which is used to obtain a part of Fourier coefficients. The other channel obtains a part of Fourier coefficients of its basis signal in the same way. To eliminate the non-ideal effects of physical components, we propose a parameters joint estimation algorithm by using the obtained Fourier coefficients. We also provide a hardware platform design scheme for implementing our system. According to simulation and hardware experiment results, the proposed system can eliminate non-ideal effects in the hardware process, and greatly improve the signal reconstruction accuracy.

Chimera

The Internet of Things (IoT) is being deployed in an ever-growing range of applications, from industrial monitoring to smart buildings to wearable devices. Each of these applications has specific computational requirements arising from their networking, system security, and edge analytics functionality. This diversity in requirements motivates the need for adaptable end-devices, which can be re-configured and re-used throughout their lifetime to handle computation-intensive tasks without sacrificing battery lifetime. To tackle this problem, this article presents Chimera, a low-power platform for research and experimentation with reconfigurable hardware for the IoT end-devices. Chimera achieves flexibility and re-usability through an architecture based on a Flash Field Programmable Gate Array (FPGA) with a reconfigurable software stack that enables over-the-air hardware and software evolution at runtime. This adaptability enables low-cost hardware/software upgrades on the end-devices and an increased ability to handle computationally-intensive tasks. This article describes the design of the Chimera hardware platform and software stack, evaluates it through three application scenarios, and reviews the factors that have thus far prevented FPGAs from being utilized in IoT end-devices.

Research on Green Habitat Design Based on Field Wireless Sensing Hazardous Substance Detection

Field wireless sensor network is the current global engineering field research hotspot for structural health monitoring wireless sensor network that is one of the important branches to real‐time monitoring of the safety status of the upper wood engineering structure to avoid the occurrence of many safety accidents caused by major structural and equipment damage and to guide the maintenance of major structures; the establishment of a wireless sensor network system is one of the current research priorities. This paper researches and designs a wireless sensor network system level scheme for structural health monitoring that is divided into two parts based on the hardware platform design and software development based on the system that focuses on the time synchronization protocol and synchronous acquisition method featuring synchronous acquisition start time scheme, time separation method, and flexible optimization model of time information. The method applies to high‐frequency acquisition to guarantee the time of sampling points in structural environmental measurement. The accuracy of the information and the reliability of the field diagnosis, for the detection of harmful substances, as well as leading to the construction of green habitat environment have a qualitative leap, for the design of green habitat environment that has enough progress.

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Modern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, which development and management is not that straightforward. Despite acceleration and flexibility are desirable in many domains, the barrier of hardware deployment and operation is still there since specific advanced expertise and skills are needed. Related challenges are effectively tackled by leveraging on automation strategies that in some cases, as in the proposed work, exploit model-based approaches.This paper is focused on the Multi-Dataflow Composer (MDC) tool, that intends to solve issues related to design, optimization and operation of coarse-grain reconfigurable hardware accelerators and their easy adoption in modern heterogeneous substrates. MDC latest features and improvements are introduced in detail and have been assessed on the so far unexplored robotics application field. A multi-profile trajectory generator for a robotic arm is implemented over a Xilinx FPGA board to show in which cases coarse-grain reconfiguration can be applied and which can be the parameters and trade-offs MDC will allow users to play with.

Design of elevator control system based on DE10-Nano board

In today’s society, the elevator has become an indispensable tool in people’s production and life. Due to the obvious advantages of FPGA in digital circuit control system, the control based on FPGA has become one of the most widely used control methods of elevator. DE10-Nano board provides a powerful hardware design platform based on Intel system on chip (SoC) FPGA, which can flexibly and conveniently complete the elevator control function. In this paper, based on DE10-Nano board, the function analysis and design of elevator control system are completed, and the effectiveness of the control system function is verified through time sequence simulation.

A Flexible, Low-Power Platform for UAV-Based Data Collection From Remote Sensors

This article presents the design and characterisation of a new low-power hardware platform to integrate unmanned aerial vehicle and wireless sensor technologies. In combination, these technologies can overcome data collection and maintenance problems of in situ monitoring in remote and extreme environments. Precision localisation in support of maximum efficiency mid-range inductive power transfer when recharging devices and increased throughput between drone and device are needed for data intensive monitoring applications, and to balance proximity time for devices powered by supercapacitors that recharge in seconds. The platform described in this article incorporates ultra-wideband technology to achieve high-performance ranging and high data throughput. It enables the development of a new localisation system that is experimentally shown to improve accuracy by around two orders of magnitude to 10 cm with respect to GNSS and achieves almost 6 Mbps throughput in both lab and field conditions. These results are supported by extensive modelling and analysis. The platform is designed for application flexibility, and therefore includes a wide range of sensors and expansion possibilities, with source code for two applications made immediately available as part of a open source project to support research and development in this new area.

Direct Current Charger Hardware Platform Design

In order to reduce the pollution caused by fuel vehicles to the environment, electric vehicles are becoming the means of transportation. The replacement of fuel vehicles by electric vehicles is a future trend. Based on practical requirements, a 120 kW direct current charger has been designed. Taking the MK60DN512 as the core controller, a direct current charger control system is designed and implemented. The overall solution of the direct current charger control system is designed. According to the functional requirements of the direct current charger, a system hardware platform is built based on embedded technology. The hardware mainly consists of MK60DN512 microcontroller, start/reset circuit, JTAG download/debugging circuit, clock circuit, minimum system power supply, output voltage sampling and signal conversion circuit, output current sampling and signal conversion circuit, AC relay control circuit and temperature detection circuit.

Hardware Platform Design for Baseband Data Transmission of WCDMA Based on USB3.0

This paper proposes a hardware platform for WCDMA baseband data transmission, which consists of USB3.0 interface, general purposes processor (GPP), and software defined radio (SDR) system. In view of the requirements of WCDMA system, the hardware platform consisting of USB3.0 controller, FPGA and DDRII was selected, which finally realized the high throughput rate and low delay transmission of baseband data of WCDMA system. The experimental results show that in this GPP software defined radio system, the interface speed of USB3.0 can reach 200MBps, and the loopback delay time of the system is about 0.7ms, which can meet the requirements of WCDMA system.

A Teaching Content Design of Embedded System in Accordance with the Characteristics of the Computer Science

Embedded system is developing rapidly, and the embedded system course is becoming a standard teaching configuration for both electronic and computer majors at home and abroad. Aimed at computer science, this article analyzes each knowledge point of embedded system course from the definition and composition of embedded system, on the basis of the relevant knowledge system, and finally gives a design of teaching content for embedded system. This teaching content emphasizes the function of the embedded operating system, which separates from the single chip microcomputer system and excludes the situation that the application and operating system are integrated together. The embedded hardware teaching emphasizes the design of hardware platform based on embedded processor and focus on the overall design ideas and framework design. And the teaching of embedded software system discusses the development environment for embedded operating system and the driver system design based on embedded operating system as well as GUI, and PMD, in order to further standardize the teaching of embedded system in computer science and to cultivate the talents of embedded system which are more in line with the needs of the society.

Building the Internet of Things with bluetooth smart

The Internet of Things, or the IoT, is an emerging, disruptive technology that enables physical devices to communicate across disparate networks. IP has been the de facto standard for seamless interconnectivity in the traditional Internet; and piggybacking on the success of IP, 6LoWPAN has been the first standardized technology to realize it for networks of resource-constrained devices. In the recent past Bluetooth Low Energy (BLE) a.k.a Bluetooth Smart - a subset of the Bluetooth v4.0 and the latest v4.2 stack, has surfaced as an appealing alternative, with many competing advantages over available low-power communication technologies in the IoT space such as IEEE 802.15.4. However, BLE is a closed standard and lacks open hardware and firmware support, something that hinders innovation and development in this field. In this article, we aim to overcome some of the constraints in BLE’s core building blocks by making three contributions: first, we present the design of a new open hardware platform for BLE; second, we provide a Contiki O.S. port for the new platform; and third, we identify research challenges and opportunities in 6LoWPAN-connected Bluetooth Smart. We believe that the knowledge and insights will facilitate IoT innovations based on this promising technology.

Design and Implementation of Galaxian Game Based on FPGA Architecture

With the development of computer and network technology, the pace of peoples life is more and more fast. At the same time, the need in the entertainment is also growing. The game based on handheld is becoming more and more popular. It has been booming along with the development of its educational, fun, casual, easy to carry, easy to operate, highly interactive and many other features to meet the people's entertainment needs.This paper introduces the embedded systems based on general-purpose software development model and development process, including the design of hardware platform and software. The design of the hardware platform is the QuartusII10.1, the software platform is Nios II EDS 10.1 and the programming language is C and VHDL. Based on the SPOC Builder tool, we designed the reconfigurable IP cores of the VGA display, LTM touch screen. With Galaxian game as an example, we design a embedded game based on GUI. The results show that the game system is friendly human-computer interaction and quick response and action. This configurable IP core is highly flexibility, variability, plasticity and it can achieve more functional expansion and development in the same resource.

Embedded motion controller design based on RTEX network

Adopting embedded framework and network communication mode,a kind of multi-axis embedded motion controller hardware platform design for Panasonic A5N drive was proposed,which was based on the modular control core(ARM + FPGA) and could adapt to the new real-time network communication named RTEX. It was transplanted inμC/OS-Ⅱ. The processes of controller's functional design,hardware design and software design were explained in detail. Up to now,the motion controller's hardware platform had been completed and verified by communication experiments and position and velocity control experiments based on SCARA robot. The experimental results show that the controller has good communication function and stable performance,and can well accomplish the functions of servo control.

Design of Driving Circuit of Area Array CCD with Interline Transfer Based on FPGA

In this paper, FPGA is chosen as the hardware design platform, on the base of sufficient analysis of ICX204AL's working principle and driving timing, the driving timing of CCD is described with Verilog HDL in the development environment of QuartusII 9.0. Finally, Modelsim SE 6.4a is employed to carry on the simulation to verify the accuracy of the design. The result shows that the driving circuit design can meet the demands of ICX204AL, and the CCD can work stably.

Detection of scale-freeness in brain connectivity by functional MRI: Signal processing aspects and implementation of an open hardware co-processor

An outstanding issue in graph-theoretical studies of brain functional connectivity is the lack of formal criteria for choosing parcellation granularity and correlation threshold. Here, we propose detectability of scale-freeness as a benchmark to evaluate time-series extraction settings. Scale-freeness, i.e., power-law distribution of node connections, is a fundamental topological property that is highly conserved across biological networks, and as such needs to be manifest within plausible reconstructions of brain connectivity. We demonstrate that scale-free network topology only emerges when adequately fine cortical parcellations are adopted alongside an appropriate correlation threshold, and provide the full design of the first open-source hardware platform to accelerate the calculation of large linear regression arrays.

红外预警实时图像处理系统设计与实现

A platform of real-time image processing is applied to scanning infrared-warning system.The platform is consisted of FPGA in Virtex-5 series of Xilinx and the high-speed DSP TMS320C6455 of TI based multi-core architecture.In order to improve the real-time of the system,a multi-channel scanning mechanism is introduced to the FPGA inner to replace the waiting mechanism adopted in traditional scanning infrared-warning real-time image processing system.The SRIO protocol is applied among the processors to attain high-speed communication,and the processed data is transferred to the master computer by PCI-e mode.Experimental results show that hardware platform design of this system meets the real-time needs and is more developed than the traditional one on delay time,false-warning and miss-warning.

The Study of Electromagnetic Slip Clutch Application in Step Less Speed Regulation of Small Cars

For the current situation of automatic transmission technology which applied to small cars, it proposes a concept that electromagnetic slip clutch achieves step less speed regulation of small cars, describes its technical principle and feasibility, analysis the mechanical properties of electromagnetic slip clutch, at sometimes, the article proposes mathematical modeling technology for the electronic control system of electromagnetic slip clutch, and structures software and hardware design platform with C and 32 microcontroller. Finally, it confirms the research value of electromagnetic slip clutch for the step less speed regulation of small cars.

Design and Improvement of Host and Backup Selection

In order to resist the Single Event Upset（SEU）in outer space so that the camera focal plane array system could work in a long time, a design and improvement method for the selection of host and backup based on FPGA was introduced. VHDL was used to do the design and simulation, FPGA developed by Altera company was chosen as the hardware design platform. The results of experiment showed that the improved module could reliably get a group of effective data from the two in all cases and the camera focal plane array system could produce reliable driving timing for the CCD camera.