Abstract
Macro scale synchronous electrostatic machines (SEMs) require medium voltage (5kV) and high fundamental frequencies (high pole number ~ 96) to be competitive with traditional electromagnetic machines. This paper focuses on the design, modeling, and characterization of a medium voltage current source inverter hardware platform to meet the low current and high frequency requirements of SEMs. The inverter stage utilizes JFET super cascodes for the medium voltage switches. A full-bridge front end regulates the necessary dc-link current and provides some of the voltage gain from the low voltage dc input. A sensitivity analyses shows that the system losses have a quadratic dependence on output voltage and a linear dependence on switching frequency and dc-link current. Minimal dependence on output power and fundamental frequency were measured. Averaged modeling shows a right-half-plane pole exists for the dc-link control. Two methods for stabilizing the machine drive were proposed and validated. Active damping via virtual resistance on the dc link was used to shift the pole to the left half plane. The second method utilizes q-axis voltage decoupling to remove the voltage disturbance of the inverter controller on the dc-link current. The impacts on system stability and disturbance rejection were measured and correlate with modeling.
Highlights
Electrostatic machines have attracted interest over the years for various applications, ranging from MEMS-scale micro motors for miniaturized pumps and turbines [1], linear actuator machines [2], up to megawatt scale design analysis for power generation [3][4]
To improve the torque density gap, research has focused on increasing the surface area, utilizing a liquid optimized for field breakdown, permittivity and viscosity, and embracing high pole counts and medium voltage designs [5]
This has culminated in a threephase separately excited synchronous electrostatic machine (SEM) that is competitive with air cooled modern electromagnetic machines in torque density and has order of magnitude lower electrical loss [5]
Summary
This paper focuses on the design, modeling, and characterization of a medium voltage current source inverter hardware platform to meet the low current and high frequency requirements of SEMs. The inverter stage utilizes JFET super cascodes for the medium voltage switches. A sensitivity analyses shows that the system losses have a quadratic dependence on output voltage and a linear dependence on switching frequency and dc-link current. Averaged modeling shows a right-half-plane pole exists for the dclink control. The second method utilizes q-axis voltage decoupling to remove the voltage disturbance of the inverter controller on the dc-link current. Inverter d axis modulation depth Rotor electrical frequency [rad/s] Voltage regulator proportional and integral gains, [ − ] [( sec)-1] Current regulator proportional and integral gains, [ ] [( sec)]
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