Design Of Frequency Synthesizer Research Articles

Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <–103-dBc Spurious Tones Using Digital Spur Cancellation

Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <–103-dBc Spurious Tones Using Digital Spur Cancellation

Optimized Design of Direct Digital Frequency Synthesizer Based on Hermite Interpolation

To address the issue of suboptimal spectral purity in Direct Digital Frequency Synthesis (DDFS) within resource-constrained environments, this paper proposes an optimized DDFS technique based on cubic Hermite interpolation. Initially, a DDFS hardware architecture is implemented on a Field-Programmable Gate Array (FPGA); subsequently, essential interpolation parameters are extracted by combining the derivative relations of sine and cosine functions with a dual-port Read-Only Memory (ROM) structure using the cubic Hermite interpolation method to reconstruct high-fidelity target waveforms. This approach effectively mitigates spurious issues caused by amplitude quantization during the DDFS digitalization process while reducing data node storage units. Moreover, this paper introduces single-quadrant ROM compression technology to further diminish the required storage space. Experimental results indicate that, compared to traditional DDFS methods, the optimization scheme proposed in this work achieves a ROM resource compression ratio of 1792:1 and a 14-bit output Spurious-Free Dynamic Range (SFDR) of −88.134 dBc, effectively enhancing amplitude quantization precision and significantly lowering spurious levels. This significantly improves amplitude quantization precision and reduces spurious levels. The proposed scheme demonstrates notable advantages in both spectral performance and resource utilization efficiency, making it highly suitable for resource-constrained embedded systems and high-performance applications such as radar and communication systems.

Design and Implementation of C-Band Frequency Synthesizer Using LMX2592 IC

The paper presents the design scheme and implementation of a PLL-based-frequency synthesizer using LMX2592 IC. The frequency synthesizer have vital role in the development of up-converter and down-converter equipments. Therefore, on the RT-Duroid RO4350 substrate, a low phase noise and stable carrier generator is designed and implemented. Graphical User Interface (GUI) & LAN based programming is developed to easily change the synthesizer frequency. The control system analysis using root locus and bode plot is presented for system stability.The experimental results representing the performance parameters, like frequency range, frequency step size, output power, phase noise, carrier stability, harmonics, and spurious, etc., are also presented in the paper. The analysis of spurious and phase noise performance at near integer boundary conditions are done by changing loop bandwidth and phase margin.

The Design of a Millimeter-Wave Frequency Synthesizer [The Analog Mind

We have previously described the design of a voltage-controlled oscillator (VCO) and a multimodulus divider (MMD) for the 30-GHz range <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> , <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> . In this article, we extend our work to develop a millimeter-wave integer-N frequency synthesizer.

Design of Digital Frequency Synthesizer for 5G SDR Systems

The previous frequency synthesizer techniques for scalable SDR are not compatible with high end applications due to its complex computations and the intolerance over increased path interference rate which leads to an unsatisfied performance with improved user rate in real time environment. Designing an efficient frequency synthesizer framework in the SDR system is essential for 5G wireless communication systems with improved Quality of service (QoS). Consequently, this research has been performed based on the merits of fully digitalized frequency synthesizer and its explosion in wide range of frequency band generations. In this paper hardware optimized reconfigurable digital base band processing and frequency synthesizer model is proposed without making any design complexity trade-off to deal with the multiple standards. Here fully digitalized frequency synthesizer is introduced using simplified delay units to reduce the design complexity. Experimental results and comparative analyzes are carried out to validate the performance metrics and exhaustive test bench simulation is also carried out to verify the functionality.

Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing

5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2.

A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer

High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.

Design of a spurious-free RF frequency synthesizer for fast-settling receivers

A tunable reference clock frequency topology is presented as a spur reduction application for frequency synthesizers of fast frequency hopping spread spectrum systems. The method was verified by measurements on a designed hardware operating at L-band frequencies. This spur reduction method is based on optimizing the reference clock frequency of synthesizers to mitigate spurs. By using the spur reduction method, the power of spurious signals was reduced up to 57 dB. The performance of the spur reduction method was also analyzed at different loop-filter configurations. Smaller lock time was obtained by enlarging the bandwidth of the loop filter up to 150 kHz. The required power response of the spurious signals specified in telecommunication standards was achieved even though the loop filter bandwidth was enlarged.

A Programmable Frequency Divider With a Full Modulus Range and 50% Output Duty Cycle

Programmable frequency dividers with wide modulus range and 50% output duty cycle are highly desirable in the design of frequency synthesizers and phase-locked loops. However, most of the conventional dividers cannot simultaneously achieve a 50% output duty cycle and full modulus range. A programmable frequency divider with a full modulus range, 50% output duty cycle and low phase noise is presented in this paper. To achieve a 50% output duty cycle, the divider employs a novel programmable down-counter based on a modified D flip-flop with a load function. The divider, which was fabricated in a standard 0.18-μm CMOS process, achieves a full 1 to 256 modulus range, 50% output duty cycle, and can operate up to 2.3 GHz with a 1.8-V supply voltage and a power consumption of 3.4 mW. The measured phase noise is -141 dBc/Hz at the frequency offset of 1 MHz when the divider is working at a 1-GHz operational frequency and a division ratio of 10.

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer

Due to the advantages of fast frequency shifting, continuous phase shifting, fine frequency resolution, large bandwidth, and excellent spectral purity, the direct digital frequency synthesis (DDFS) technique is attracting more attention than ever before. Although the DDFS suffer from high power consumption, recent researches on the development of the low power DDFS (LP-DDFS) increases the feasibility of applying the DDFS to portable devices. To further accelerate the use of LP-DDFS, a new LP-DDFS design to significantly improve power efficiency is proposed and analyzed in this paper. In the new design, the dominant spur by truncation errors causing performance degradation has been also thoroughly considered. Since the existing dithering techniques for the truncation error problems can cause the additional performance degradation due to the side effects such as frequency offset and SNDR deterioration, an enhanced dithering technique is also proposed in this paper. The proposed technique includes a frequency compensation circuit and thus minimizes the truncation errors in the LP-DDFS with the minimal additional power consumption and SNDR degradation. Both theoretical and experimental analysis are conducted to verify the proposed design, where a prototype chip is fabricated and measured.

Power-effective ROM-less DDFS Design Approach with High SFDR Performance

A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

10-15 Frequency Stability Microwave Synthesizer for Atomic Fountain Frequency Standard

This paper presents the design and phase noise measurement of microwave frequency synthesizer for atomic fountain frequency standard. In this synthesizer, a voltage-controlled DRO is locked to 100MHz hydrogen maser signal through a divider chain. The required interrogation frequency 9192631770 Hz is generated by mixed with 7368230 Hz and 400 MHz signals. The experimental results show that the phase noise of interrogation signal at 9.192 GHz is -88dBc/Hz@ offset 1Hz. With such performances, the expected Dick effect contribution to atom fountain frequency standard is reported at a level of 1.0×10-15 at 1 s integrating time, that is a factor 10 higher than quantum noise limit of atom frequency standard. The carrier spectral spur of microwave synthesizer signal impacted on atomic fountain frequency standard is also discussed.

Research on High Performance Frequency Synthesizer in Radio Frequency Integrated Circuits

With the popularization of broadcasting networks, telecommunication networks, and Internet triple play services, broadband requirements have been proposed for transceivers in wireless communication systems. Frequency source is an important part of the RF transceiver, which is usually chosen as the source of the transceiver frequency reference source. Therefore, the development of ultra-wideband, high stability, low phase noise, and low spurious performance of the frequency synthesizer is of great significance. This paper firstly analyzed the transmission process of noise in phase-locked loop by establishing a linear mathematical model of phase locking loop (PLL), and then studied the main factors affecting the phase noise and spurious performance in the application design. In order to meet the demand of triple-miniaturized RF front end, an integrated phase-locked chip is used to design a frequency synthesizer, where the output frequency of the two channels ranges from 137.5 MHz to 4.4 GHz. In order to meet the engineering application requirements, the frequency synthesizer is designed with a host computer to achieve the programmable control of the output frequency and output power. Finally, the optimized design of a wideband frequency synthesizer is provided to make up for the lack of performance of the integrated phase-locked chip design, of which the output frequency range is 31.25 MHz ~8 GHz, including basic PLL module circuit, power control module circuit, and frequency expansion module circuit.

Design of 0.35-ps RMS Jitter 4.4–5.6-GHz Frequency Synthesizer with Adaptive Frequency Calibration Using 55-nm CMOS Technology

This paper demonstrates the design and implementation of a 5-GHz frequency synthesizer using 55-nm complementary metal-oxide semiconductor technology. The proposed synthesizer achieves an ultra-low 0.35-ps jitter with a high-resolution adaptive frequency calibration scheme that automatically chooses frequency-tuning curves and improves calibration accuracy. The proposed synthesizer employs a high-Q LC voltage-controlled oscillator, constant bandwidth, low, and even $$K_{\mathrm{VCO}}$$ technique using thermometer-weighted capacitor calibration, a low-power divider, and a charge-pump (CP) circuit to achieve low jitter. The oscillator comprises a modified digitally controlled capacitor and varactor array, which extend the tuning range and minimize the phase noise. A matched differential CP is adopted to reduce reference spurs and phase-noise performance. The proposed frequency synthesizer achieves an output frequency of 4.4–5.6 GHz with a chip area of $$0.33\hbox { mm}^{2}$$ . The power consumption is 20 mW from a 1.2-V supply at 5 GHz, and the reference spur is −67.99 dBc. The measured root mean-square random jitter and phase noise are 0.35 ps and −110.04 dBc/Hz at 1 MHz, respectively.

Low Phase Noise Frequency Synthesis for Ultrastable $X$ -Band Oscillators

In this letter, the design of a low phase noise frequency synthesizer is presented. The synthesizer was designed to produce four frequencies: 10 MHz, 100 MHz, 1 GHz and 10 GHz. The 1-GHz signal is produced by frequency division whereas the 100-MHz output is generated by phase-locking a low phase noise oscillator to the 1-GHz signal, hence significantly reducing its phase noise. Both residual and total phase noise measurements are presented.

A novel power-efficient high-speed clock management unit using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is one of the most attractive alternatives for complementary metal-oxide semiconductor technology. The QCA widely supports a new paradigm in the field of nanotechnology that has the potential for high density, low power, and high speed. The clock manager is an essential building block in the new microwave and radio frequency integrated circuits. This paper describes a novel QCA-based clock management unit (CMU) that provides innovative clocking capabilities. The proposed CMU is achieved by utilizing edge-triggered D-type flip-flops (D-FFs) in the design of frequency synthesizer and phase splitter. Edge-triggered D-FF structures proposed in this paper have the successful QCA implementation and simulation with the least complexity and power dissipation as compared to earlier structures. The frequency synthesizer is used to generate new clock frequencies from the reference clock frequency based on a combination of power-of-two frequency dividers. The phase splitter is integrated with the frequency synthesizer to generate four clock signals that are 90o out of phase with each other. This paper demonstrates that the proposed QCA CMU structure has a superior performance. Furthermore, the proposed CMU is straightforwardly scalable due to the use of modular component architecture.

A fast and efficient constant loop bandwidth with proposed PFD and pulse swallow divider circuit in [formula omitted] fractional-N PLL frequency synthesizer

This work presents the design of a ΔΣ fractional-N PLL frequency synthesizer with a new loop bandwidth calibration and automatic frequency control (AFC) circuit, applicable for wide band RF communication system. This new and unique loop bandwidth calibration circuit has been implemented using logarithmic and anti-logarithmic (Base2) architecture. This architecture is an efficient design technique as well as faster operation in CMOS domain. The operating frequency range of the ΔΣ fractional-N PLL frequency synthesizer is from 2.158 to 5.133GHz. The variation of LC VCO gain (KVCO) is obvious due to wide band application and it varies from 30.65MHz/Volt to 368MHz/Volt for the frequency range of 2.158–5.133GHz. Constant loop bandwidth is maintained by controlling the charge pump current. Power consumption of the ΔΣ fractional-N PLL frequency synthesizer is 34mW from a 1.2Volt power supply and the work has been carried out in 0.13μm standard CMOS process. Also, this design includes an automatic frequency control unit for the LC VCO circuit which is coarsely tuned within 1.825μs for KVFC=10 for worst case condition and it completes the loop bandwidth (LBW) calibration within 7.84μs for KLBC=150 for worst case condition. The maximum locking time of the ΔΣ fractional-N PLL frequency synthesizer with loop bandwidth calibration and automatic frequency control circuit is 12.7μs for KVFC=10 and KLBC=150 for worst case condition. The ΔΣ fractional-N PLL is locked much faster than any work reported earlier using the proposed PFD, CP, proposed pulse swallow divider, efficient AFC circuit for LC VCO and a new loop BW calibration technique in transistor level simulation using Cadence SpectreRF. The main advantage of this loop bandwidth calibration technique is that the calibration time can be adjusted according to the PLL output frequency, loop bandwidth calibration accuracy and tuning frequency range of the LC VCO.

A Low-Power Design of Delta-Sigma Based Digital Frequency Synthesizer for Bio Sensor Networks

A Low-Power Design of Delta-Sigma Based Digital Frequency Synthesizer for Bio Sensor Networks

Direct Digital Frequency Synthesizer Designs in MATLAB

This study presents the structure of the Direct Digital Frequency Synthesizers (DDFSs) which have several advantages compared to conventional synthesizers such as high frequency, fast switching speed and low power dissipations. In order to lessen the physical area and power dissipation, ROM compression techniques are applied in designs. Bipartite Table Method (BTM) and Multipartite Table Method (MTM) are utilized in this study because of the fact that they provide high compression rates. By using MTM, the compression rates of 157.54:1, 726.71:1 and 3463.29:1 are obtained at 58.40 dB, 75.30 dB and 84.66 dB SFDR levels, respectively.

A Multi-Frequency Multi-Standard Wideband Fractional- PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards

This paper presents a wideband fractional- $ { N}$ frequency synthesizer design with a low-effort adaptive calibration technique for $\Sigma \Delta $ quantization noise cancellation. After adopting from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital–analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications.