Decoder Design Research Articles

Minimum-Integer Computation Finite Alphabet Message Passing Decoder: From Theory to Decoder Implementations towards 1 Tb/s

In Message Passing (MP) decoding of Low-Density Parity Check (LDPC) codes, extrinsic information is exchanged between Check Nodes (CNs) and Variable Nodes (VNs). In a practical implementation, this information exchange is limited by quantization using only a small number of bits. In recent investigations, a novel class of Finite Alphabet Message Passing (FA-MP) decoders are designed to maximize the Mutual Information (MI) using only a small number of bits per message (e.g., 3 or 4 bits) with a communication performance close to high-precision Belief Propagation (BP) decoding. In contrast to the conventional BP decoder, operations are given as discrete-input discrete-output mappings which can be described by multidimensional LUTs (mLUTs). A common approach to avoid exponential increases in the size of mLUTs with the node degree is given by the sequential LUT (sLUT) design approach, i.e., by using a sequence of two-dimensional Lookup-Tables (LUTs) for the design, leading to a slight performance degradation. Recently, approaches such as Reconstruction-Computation-Quantization (RCQ) and Mutual Information-Maximizing Quantized Belief Propagation (MIM-QBP) have been proposed to avoid the complexity drawback of using mLUTs by using pre-designed functions that require calculations over a computational domain. It has been shown that these calculations are able to represent the mLUT mapping exactly by executing computations with infinite precision over real numbers. Based on the framework of MIM-QBP and RCQ, the Minimum-Integer Computation (MIC) decoder design generates low-bit integer computations that are derived from the Log-Likelihood Ratio (LLR) separation property of the information maximizing quantizer to replace the mLUT mappings either exactly or approximately. We derive a novel criterion for the bit resolution that is required to represent the mLUT mappings exactly. Furthermore, we show that our MIC decoder has exactly the communication performance of the corresponding mLUT decoder, but with much lower implementation complexity. We also perform an objective comparison between the state-of-the-art Min-Sum (MS) and the FA-MP decoder implementations for throughput towards 1 Tb/s in a state-of-the-art 28 nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology. Furthermore, we demonstrate that our new MIC decoder implementation outperforms previous FA-MP decoders and MS decoders in terms of reduced routing complexity, area efficiency and energy efficiency.

Innovation in Constrained Codes

Constrained coding is a somewhat nebulous term which we may define by either inclusion or exclusion. A constrained system is defined by a constrained set of “good” or “allowable” sequences to be recorded or transmitted. Constrained coding focuses on the analysis of constrained systems and the design of efficient encoders and decoders that transform arbitrary user sequences into constrained sequences. Constrained coding has extensively been used since the advent in the 1950s of digital storage and communication devices. They have found application in all hard disk, non-volatile memories, and optical discs, such as CD, DVD, and Blu-Ray Disc, and they are now projected for usage in DNA-based storage. We survey theory and practice of constrained coding, tracing the evolution of the subject from its origins in Shannon's classic 1948 paper to present-day applications in DNA-based data storage systems.

An Information-Theoretic Perspective on Successive Cancellation List Decoding and Polar Code Design

This work identifies information-theoretic quantities that are closely related to the required list size on average for successive cancellation list (SCL) decoding to implement maximum-likelihood decoding over general binary memoryless symmetric (BMS) channels. It also provides upper and lower bounds for these quantities that can be computed efficiently for very long codes. For the binary erasure channel (BEC), we provide a simple method to estimate the mean accurately via density evolution. The analysis shows how to modify, e.g., Reed-Muller codes, to improve the performance when practical list sizes, e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L\in {[{8, 1024}]}$ </tex-math></inline-formula> , are adopted. Exemplary constructions with block lengths <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N\in \{128,512\}$ </tex-math></inline-formula> outperform polar codes of 5G over the binary-input additive white Gaussian noise channel. It is further shown that there is a concentration around the mean of the logarithm of the required list size for sufficiently large block lengths, over discrete-output BMS channels. We provide the probability mass functions (p.m.f.s) of this logarithm, over the BEC, for a sequence of the modified RM codes with an increasing block length via simulations, which illustrate that the p.m.f.s concentrate around the estimated mean.

Performance Analysis and Receiver Design of Spatio-Temporal Coded Modulation Scheme for Diffusion-Based Molecular MIMO Systems

Diffusion-based molecular communication (DBMC) systems allow messenger molecules to reach the intended receiver using laws of diffusion. The Brownian motion of messenger molecules introduces delay in the system causing the problem of inter-symbol interference (ISI). Along with ISI, the problem of inter-link interference (ILI) comes into picture in the diffusion-based molecular multiple-input multiple-output (DB-MoMIMO) systems. To combat against ISI and ILI issues, index modulation (IM) approaches are recently proposed in the literature for improving the performance of DB-MoMIMO systems. Despite the existence of IM approaches, problems of ISI and ILI still persist due to the slow random motion of molecules in DB-MoMIMO channels. Motivated by this, a novel coded modulation approach called molecular spatio-temporal coded modulation (MSTCM) is proposed in this paper which shows promising improvement in the performance of DB-MoMIMO systems by encoding the information both in space and time axes. Further, if system has access to two types of molecules, the dual-type modulation schemes are discussed for the same. Moreover, the encoder and decoder designs for the proposed mapping strategy are provided. In addition, a theoretical bit error rate expression for the MSTCM scheme is derived and simulation results are shown to corroborate the theoretical ones.

Energy-Efficient 2×4 and 3×8 QCA-Based Decoder Designs

QCA technology is a promising technology for implementing compact, energy-efficient and high-speed nano-scale digital circuits. This paper proposes various single-and multi-layer 2×4 and 3×8 QCA-based decoder structures. These structures are implemented based on a compact and energy-efficient cell interaction-based 2×4 uncontrollable decoder. The proposed structures are extensively simulated and evaluated using specialized QCA design tools. Simulation results show that the proposed structures have outperformed their recently reported counterparts and have achieved significant improvements in key design parameters including cell count, area, and energy dissipation. For instance, the proposed multi-layer 2×4 and 3×8 decoders have achieved up to 34% and 30% enhancements in cell count, 33% and 33% reductions in area requirements besides 44% and 27% improvements in energy dissipation, respectively as compared to their best existing counterparts. Hence, the proposed QCA-based decoders can serve as compact and energy-efficient building blocks for larger digital systems.

Determining quantum topological semion code decoder performance and error correction effectiveness with reinforcement learning

Quantum error correction technology is a vital method to eliminate noise during the operation of quantum computers. To solve the problem caused by noise, in this paper, reinforcement learning is used to encode defects of Semion codes, and the experience replay technique is used to realize the design of decoder. Semion codes are quantum topological error correction codes with the same symmetry group Z2 as Kitaev toric codes, we used the topological characteristics of error correction codes to map qubits to multi-dimensional space, and error correction accuracy of the decoder is calculated to be 77.5%. Calculate the threshold of topological quantum Semion code, depending on the code distance, resulting in different thresholds, pthreshold = 0.081574 when the code distance is d = 3, 5, 7 and threshold pthreshold = 0.09542 when the code distance is d = 5, 7, 9. And we design the Q-network to optimize the cost of quantum circuit gates and compare the size of the cost reduction under different thresholds. Reinforcement learning is an important method for designing Semion code decoders and optimizing numerical values, providing more general error models and error correction codes for future machine engineering decoders.

Design of LUT-Based LDPC Decoders for Spin-Transfer Torque Magnetic Random Access Memory

Recently, low-density parity-check (LDPC) codes have been proposed to improve the reliability of spin-transfer torque magnetic random access memory (STT-MRAM). While several research works focus on the design of LDPC codes to combat the process variation and thermal fluctuation of the STT-MRAM, we aim to tackle the high decoding latency issues by the novel design of a lookup table (LUT)-based LDPC decoder for the forward and backward (FB) processes. In this work, the channel quantizer and LUT operations of the LDPC decoder are jointly designed by minimizing the error probability estimated from the density evolution (DE) algorithm. The simulation results show that the proposed design method for a code rate of 0.9 outperforms the previous methods in terms of bit error rate (BER) performance. Furthermore, the proposed design can support the channel model of the STT-MRAM without an independent and identically distributed (i.i.d.) channel adapter.

Spike prediction on primary motor cortex from medial prefrontal cortex during task learning

Objectives. Brain–machine interfaces (BMIs) aim to help people with motor disabilities by interpreting brain signals into motor intentions using advanced signal processing methods. Currently, BMI users require intensive training to perform a pre-defined task, not to mention learning a new task. Thus, it is essential to understand neural information pathways among the cortical areas in task learning to provide principles for designing BMIs with learning abilities. We propose to investigate the relationship between the medial prefrontal cortex (mPFC) and primary motor cortex (M1), which are actively involved in motor control and task learning, and show how information is conveyed in spikes between the two regions on a single-trial basis by computational models. Approach. We are interested in modeling the functional relationship between mPFC and M1 activities during task learning. Six Sprague Dawley rats were trained to learn a new behavioral task. Neural spike data was recorded from mPFC and M1 during learning. We then implement the generalized linear model, the second-order generalized Laguerre–Volterra model, and the staged point-process model to predict M1 spikes from mPFC spikes across multiple days during task learning. The prediction performance is compared across different models or learning stages to reveal the relationship between mPFC and M1 spike activities. Main results. We find that M1 neural spikes can be well predicted from mPFC spikes on the single-trial level, which indicates a highly correlated relationship between mPFC and M1 activities during task learning. By comparing the performance across models, we find that models with higher nonlinear capacity perform significantly better than linear models. This indicates that predicting M1 activity from mPFC activity requires the model to consider higher-order nonlinear interactions beyond pairwise interactions. We also find that the correlation coefficient between the mPFC and M1 spikes increases during task learning. The spike prediction models perform the best when the subjects become well trained on the new task compared with the early and middle stages. The results suggest that the co-activation between mPFC and M1 activities evolves during task learning, and becomes stronger as subjects become well trained. Significance. This study demonstrates that the dynamic patterns of M1 spikes can be predicted from mPFC spikes during task learning, and this will further help in the design of adaptive BMI decoders for task learning.

Finite Rate QLDPC-GKP Coding Scheme that Surpasses the CSS Hamming Bound

Quantum error correction has recently been shown to benefit greatly from specific physical encodings of the code qubits. In particular, several researchers have considered the individual code qubits being encoded with the continuous variable GottesmanKitaev-Preskill (GKP) code, and then imposed an outer discrete-variable code such as the surface code on these GKP qubits. Under such a concatenation scheme, the analog information from the inner GKP error correction improves the noise threshold of the outer code. However, the surface code has vanishing rate and demands a lot of resources with growing distance. In this work, we concatenate the GKP code with generic quantum low-density parity-check (QLDPC) codes and demonstrate a natural way to exploit the GKP analog information in iterative decoding algorithms. We first show the noise thresholds for two lifted product QLDPC code families, and then show the improvements of noise thresholds when the iterative decoder – a hardware-friendly min-sum algorithm (MSA) – utilizes the GKP analog information. We also show that, when the GKP analog information is combined with a sequential update schedule for MSA, the scheme surpasses the well-known CSS Hamming bound for these code families. Furthermore, we observe that the GKP analog information helps the iterative decoder in escaping harmful trapping sets in the Tanner graph of the QLDPC code, thereby eliminating or significantly lowering the error floor of the logical error rate curves. Finally, we discuss new fundamental and practical questions that arise from this work on channel capacity under GKP analog information, and on improving decoder design and analysis.

Successive cancellation decoding of polar codes using new hybrid processing element

Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.

CNTFET‐based ternary address decoder design

SummaryWith the end of Moore's law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power‐ and time‐consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre‐decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs.

Design of a Bio-Inspired Gait Phase Decoder Based on Temporal Convolution Network Architecture With Contralateral Surface Electromyography Toward Hip Prosthesis Control.

Inter-leg coordination is of great importance to guarantee the safety of the prostheses wearers, especially for the subjects at high amputation levels. The mainstream of current controllers for lower-limb prostheses is based on the next motion state estimation by the past motion signals at the prosthetic side, which lacks immediate responses and increases falling risks. A bio-inspired gait pattern generation architecture was proposed to provide a possible solution to the bilateral coordination issue. The artificial movement pattern generator (MPG) based on the temporal convolution network, fusing with the motion intention decoded from the surface electromyography (sEMG) measured at the impaired leg and the motion status from the kinematic modality of the prosthetic leg, can predict four sub gait phases. Experiment results suggested that the gait phase decoder exhibited a relatively high intra-subject consistency in the gait phase inference, adapted to various walking speeds with mean decoding accuracy ranging from 89.27 to 91.16% across subjects, and achieved an accuracy of 90.30% in estimating the gait phase of the prosthetic leg in the hip disarticulation amputee at the self-selected pace. With the proof of concept and the offline experiment results, the proposed architecture improves the walking coordination with prostheses for the amputees at hip level amputation.

Turbo Product Codes for Satellite Communication: a Survey

Turbo Product Codes (TPCs) with near Shannon capacity performance especially for high code rates allow decoding operations at a speed of several Mbps or more and has low error floor. In this paper, the characteristics of TPCs as FEC code, and their suitability for being a potential candidate in satellite communication applications are discussed. Emphasis is laid to highlight TPC's flexibility in attaining different code rates, improved coding gain especially for high code rates, benefits of different types of TPC construction and decoding modifications. The need for careful amalgamation of higher order modulation techniques with TPCs to achieve good spectral and power efficiency is discussed in detail. In addition, a deep learning based approach (neural-BP) for decoding of TPCs has been discussed. This is intended to improve the parallelism in TPC decoding and to reduce the implementation complexity. It is envisaged that the neural-BP decoding approach would lead to the design of hardware efficient decoders providing high Quality of Service (QoS) in satellite communication systems.

EU‐Net: A novel semantic segmentation architecture for surface defect detection of mobile phone screens

Manual or conventional image processing algorithms are commonly used to detect surface problems on mobile phone screens. However, inefficiency and inflexibility are disadvantages. Although the semantic segmentation method has high adaptability and accuracy, it also has a low defect detection efficiency due to its excessive parameters. In order to increase defect detection efficiency, a novel efficient encoder–decoder architecture termed MB encoder–decoder architecture based on MBConv blocks, and that it reduces the number of parameters used in semantic segmentation methods i presented. In addition, by applying the MB encoder–decoder design to the U-Net, the efficient U-Net (EU-Net) is proposed. It confirms the MB encoder–decoder architecture's superiority. Then, EU-Net to mobile phone surface defect detection in real industrial scenarios. Experimental results on a dataset show the superiority of the proposed algorithm and it can meet the real-time requirement of industrial production.

Precoder and Decoder Co-Designs for Radar and Communication Spectrum Sharing.

The coexistence of radar and communication systems is necessary to facilitate new wireless systems and services due to the shortage of the useful radio spectrum. Moreover, changes in spectrum regulation will be introduced in which the spectrum is allocated in larger chunks and different radio systems need to share the spectrum. For example, 5G NR, LTE and Wi-Fi systems have to share the spectrum with S-band radars. Managing interference is a key task in coexistence scenarios. Cognitive radio and radar technologies facilitate using the spectrum in a flexible manner and sharing channel awareness between the two subsystems. In this paper, we propose a nullspace-based joint precoder–decoder design for coexisting multicarrier radar and multiuser multicarrier communication systems. The maximizing signal interference noise ratio (max-SINR) criterion and interference alignment (IA) constraints are employed in finding the precoder and decoder. By taking advantage of IA theory, a maximum degree of freedom upper bound for the -radar-communication-user interference channel can be achieved. Our simulation studies demonstrate that interference can be practically fully canceled in both communication and radar systems. This leads to improved detection performance in radar and a higher rate in communication subsystems. A significant performance gain over a nullspace-based precoder-only design is also obtained.

Design and analysis of three-dimensional m-sequence bipolar OCDMA spectral amplitude code

This paper has been focused to utilize the m-sequence (matrix) code in spectral/time/spatial OCDMA domain in a bipolar mode (Three Dimensional modes). The scheme has elegantly incorporated the design of an encoder and decoder such that the system efficiently generates the code in three-dimensional bipolar mode. The decoder design is such that it effectively suppresses the multiple user interference (MUI) of three-dimensional code. System analyses are carried for defining the BER performance variation with users acceptability and received power. The observed results demonstrate that the cardinality of m- matrix three-dimensional bipolar code is larger than the existing 3D Pascal code, 2D-MDW, 3D-PDC, 2D-PDC, 1D-CWH and 1D-MS codes. The received power in proposed system is − 5.8 dBm lesser than the 3D Pascal Code at 10–18 BER and the users in system more than 210% can be accomplished as compared to 3D Pascal code.

Group‐indexed orthogonal frequency division multiplexing index modulation aided performance trade off

In this study, a novel group-indexed orthogonal frequency division multiplexing index modulation (OFDM-IM) scheme is proposed to achieve a tradeoff between spectral efficiency (SE) and bit-error-rate (BER) performance. In the proposed scheme, the total subcarriers in a group are divided into subgroups, and additional bits are transmitted by subgroup indexing, unlike the conventional OFDM-IM scheme, which uses index bits to select active subcarriers. With the proposed scheme, the additional degree of freedom provided by the number of active subgroups selected provides a tradeoff between spectral efficiency and BER performance. Decoding is performed in steps to reduce computional complexity in the decoder design. Simulaton results show that the number of active subgroups selected influences the proposed scheme's performance in terms of energy efficiency, spectral efficiency, and BER performance.

Decoder for the Triangular Color Code by Matching on a Möbius Strip

The color code is remarkable for its ability to perform fault-tolerant logic gates. This motivates the design of practical decoders that minimise the resource cost of color-code quantum computation. Here we propose a decoder for the planar color code with a triangular boundary where we match syndrome defects on a nontrivial manifold that has the topology of a M\"{o}bius strip. A basic implementation of our decoder used on the color code with hexagonal lattice geometry demonstrates a logical failure rate that is competitive with the optimal performance of the surface code, $\sim p^{\alpha \sqrt{n}}$, with $\alpha \approx 6 / 7 \sqrt{3} \approx 0.5$, error rate $p$, and $n$ the code length. Furthermore, by exhaustively testing over five billion error configurations, we find that a modification of our decoder that manually compares inequivalent recovery operators can correct all errors of weight $\le (d-1) /2$ for codes with distance $d \le 13$. Our decoder is derived using relations among the stabilizers that preserve global conservation laws at the lattice boundary. We present generalisations of our method to depolarising noise and fault-tolerant error correction, as well as to Majorana surface codes, higher-dimensional color codes and single-shot error correction.

Three-Dimensional LiDAR Decoder Design for Autonomous Vehicles in Smart Cities

With the advancement of artificial intelligence, deep learning technology is applied in many fields. The autonomous car system is one of the most important application areas of artificial intelligence. LiDAR (Light Detection and Ranging) is one of the most critical components of self-driving cars. LiDAR can quickly scan the environment to obtain a large amount of high-precision three-dimensional depth information. Self-driving cars use LiDAR to reconstruct the three-dimensional environment. The autonomous car system can identify various situations in the vicinity through the information provided by LiDAR and choose a safer route. This paper is based on Velodyne HDL-64 LiDAR to decode data packets of LiDAR. The decoder we designed converts the information of the original data packet into X, Y, and Z point cloud data so that the autonomous vehicle can use the decoded information to reconstruct the three-dimensional environment and perform object detection and object classification. In order to prove the performance of the proposed LiDAR decoder, we use the standard original packets used for the comparison of experimental data, which are all taken from the Map GMU (George Mason University). The average decoding time of a frame is 7.678 milliseconds. Compared to other methods, the proposed LiDAR decoder has higher decoding speed and efficiency.

A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems

In this paper, a design and implementation of fixed-complexity sphere decoder (FSD) combined with interference mitigation algorithm for downlink (DL) multiuser (MU) multiple-input multiple-output (MIMO) system is presented. To overcome performance degradation from inter-user interference in DL MU-MIMO systems, a hardware friendly optimized interference mitigation algorithm is proposed. The proposed algorithm achieves 0.5 dB near-optimal performance, which is 4 dB better than existing interference whitening filter for the soft-output decision. In this paper, both hard and soft-output FSD detectors are implemented with the proposed interference mitigation algorithm to function 4 × 4 antenna MIMO detection and interference mitigation for 4 additional streams. A fully pipelined architecture is employed to support 3.6 Gbps at 150 MHz for signals modulated by 64-QAM. From the synthesis result, the designed symbol detector has a gate count of 887 K for the FSD without pre-processor and a gate count of 1220 K for interference mitigation. By comparing previously implemented MIMO detectors, the proposed design represents a promising architecture for DL MU-MIMO systems in terms of significant performance improvement relative to inter-user interference and the compatible hardware implementation maintaining high-throughput within acceptable gate count.