Decoder Design Research Articles

Design of LDPC Decoder Based On FPGA in Digital Image Watermarking Technology

LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.

An Improved Concatenation Scheme of Polar Codes With Reed–Solomon Codes

An improved Reed–Solomon (RS)-polar code concatenation scheme with a threshold is proposed. It applies successive cancellation list and hard-decision decoding based on the low-complexity chase algorithm. A new multiplicity assignment module is proposed to make it possible to realize the RS-polar code concatenation and facilitate hardware decoder design. The proposed scheme achieves high decoding performance, low decoding complexity, and short latency. The simulation results show that the improved concatenation scheme gives a coding gain reaching about 0.4 dB compared with the traditional RS-polar scheme. Moreover, it can reduce the average number of RS codewords to be decoded in a concatenated code by 65% and decrease the decoding latency by 50% when the signal-to-noise ratio is 1.75 dB.

Design of Soft VITERBI Algorithm Decoder Enhanced with Non-Transmittable Codewords for Storage Media

Design of Soft VITERBI Algorithm Decoder Enhanced with Non-Transmittable Codewords for Storage Media

Design and efficient hardware implementation schemes for non-Quasi-Cyclic LDPC codes

The design of a high-speed decoder using traditional partly parallel architecture for Non-Quasi-Cyclic (NQC) Low-Density Parity-Check (LDPC) codes is a challenging problem due to its high memory-block cost and low hardware utilization efficiency. In this paper, we present efficient hardware implementation schemes for NQCLDPC codes. First, we propose an implementation-oriented construction scheme for NQC-LDPC codes to avoid memory-access conflict in the partly parallel decoder. Then, we propose a Modified Overlapped Message-Passing (MOMP) algorithm for the hardware implementation of NQC-LDPC codes. This algorithm doubles the hardware utilization efficiency and supports a higher degree of parallelism than that used in the Overlapped Message Passing (OMP) technique proposed in previous works. We also present single-core and multi-core decoder architectures in the proposed MOMP algorithm to reduce memory cost and improve circuit efficiency. Moreover, we introduce a technique called the cycle bus to further reduce the number of block RAMs in multi-core decoders. Using numerical examples, we show that, for a rate-2/3, length-15360 NQC-LDPC code with 8.43-dB coding gain for Binary PhaseShift Keying (BPSK) in an Additive White Gaussian Noise (AWGN) channel, the decoder with the proposed scheme achieves a 23.8%-52.6% reduction in logic utilization per Mbps and a 29.0%-90.0% reduction in message-memory bits per Mbps.

FPGA design of the fast decoder for burst errors correction

The paper is about FPGA design of the fast single stage decoder for correcting burst errors during data transmission. The decoder allows correcting burst errors with 3 bits for a 15 bit codeword and a 7 bit check unit. The description of a generator polynomial search algorithm for building error-correcting codes was represented. The module structure of the decoder was designed for FPGA implementation. There are modules, such as remainder, check_pattern, decoder2, implemented by asynchronous combinational circuits without memory elements, and they process each codeword shift in parallel. Proposed implementation allows getting high performance about ∼20 ns.

Design, Simulation, and Implementation of a CMOS Analog Decoder for (480,240) Low-Density Parity-Check Code

The analog low-density parity-check (LDPC) decoder, which is a specific application of the probabilistic computing, is considered to be a promising solution for power-constrained applications. However, due to the lack of efficient electronic design automation tools and reliable circuit model, the analog LDPC decoders suffer from costly hand-craft design cycle, and are unable to provide enough coding gains for practical applications. In this paper, we present an implementation of a (480,240) CMOS analog LDPC decoder, which is the longest implemented code to date using the analog approach. We first propose an analog LDPC decoder architecture, which is constructed by the reusable modules and can significantly reduce the hardware complexity. And then, we present a mixed behavioral and structural model for the analog LDPC decoding circuits, which can reliably and efficiently predict the error-correcting performance. Finally, the experimental results show that the decoder prototype, which is fabricated in a 0.35- $\mu \text{m}$ CMOS technology, can achieve a throughput higher than 50 Mbps with the power consumption of 86.3 mW for the decoder core, and can offer a superior 6.3-dB coding gain at the bit error rate of $10^{-6}$ when the tested throughput is 5 Mbps. The proposed analog LDPC decoder is suitable for the power-limited applications with moderate throughput and certain coding gains.

VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate

In this work, we present a FPGA design and implementation of a parallel architecture of a low complexity LDPC decoder for high data rate applications. The selected code is a regular LDPC code (3, 4). VHDL design and synthesis of such architecture uses the decoding by the algorithm of BP (Believe propagation) simplified Min-Sum. The complexity of the proposed architecture was studied; it is 6335 LEs at a data rate of 2.12 Gbps for quantization of 8 bits at the second iteration. We also realized a platform based on a co-simulation on Simulink to validate performance in BER (Bit Error Rate) of our architecture.

Spatial–degree of freedom improvement of interference alignment in multi-input, multi-output interference channels

As we know, the degree of freedom approximates the capacity of a network. To improve the achievable degree of freedom in the K-user interference network, we propose a rank minimization interference minimization algorithm. Unlike the existing methods concentrating on the promotion of degree of freedom, our rank optimization method works directly with the interference matrix rather than its projection using the receive beamformers. Moreover, we put the trace constraint of the square root of desired matrix into the rank optimization to prevent the received signal-to-interference-plus-noise ratio from reduction. The decoders are designed through a weight interference leakage minimization method. Considering that the practical obtainable signal-to-noise ratio may be limited, we improve the design of decoders in rank minimization interference minimization, and propose the rank minimization rate maximization. Rank minimization rate maximization aims to reduce the impact of interference on undesired users as much as possible while improving the desired data rate. Simulation results show that rank minimization interference minimization algorithm can provide more interference-free dimensions for desired signals than other rank minimization methods. Rank minimization rate maximization outperforms rank minimization interference minimization at low-to-moderate signal-to-noise ratios, and its performance gets closer to rank minimization interference minimization with the increase in signal-to-noise ratio. Furthermore, in an improper system, rank minimization rate maximization still performs well.

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder

Low-density parity check (LDPC) error correction decoders have become popular in diverse communications systems, owing to their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into the implementation of LDPC decoder designs on field-programmable gate array (FPGA) devices, in order to exploit their high processing speed, parallelism, and re-programmability. Meanwhile, a variety of application-specific integrated circuit implementations of multi-mode LDPC decoders exhibiting both inter-standard and intra-standard reconfiguration flexibility are available in the open literature. However, the high complexity of the adaptable routing and processing elements that are required by a flexible LDPC decoder has resulted in a lack of viable FPGA-based implementations. Hence in this paper, we propose a parameterisable FPGA-based LDPC decoder architecture, which supports run-time flexibility over any set of one or more quasi-cyclic LDPC codes. Additionally, we propose an off-line design flow, which may be used to automatically generate an optimized HDL description of our decoder, having support for a chosen selection of codes. Our implementation results show that the proposed architecture achieves a high level of design-time and run-time flexibility, whilst maintaining a reasonable processing throughput, hardware resource requirement, and error correction performance.

Brain-Machine Interface Control Algorithms.

Motor brain-machine interfaces (BMI) allow subjects to control external devices by modulating their neural activity. BMIs record the neural activity, use a mathematical algorithm to estimate the subject's intended movement, actuate an external device, and provide visual feedback of the generated movement to the subject. A critical component of a BMI system is the control algorithm, termed decoder. Significant progress has been made in the design of BMI decoders in recent years resulting in proficient control in non-human primates and humans. In this review article, we discuss the decoding algorithms developed in the BMI field, with particular focus on recent designs that are informed by closed-loop control ideas. A motor BMI can be modeled as a closed-loop control system, where the controller is the brain, the plant is the prosthetic, the feedback is the biofeedback, and the control command is the neural activity. Additionally, compared to other closed-loop systems, BMIs have various unique properties. Neural activity is noisy and stochastic, and often consists of a sequence of spike trains. Neural representations of movement could be non-stationary and change over time, for example as a result of learning. We review recent decoder designs that take these unique properties into account. We also discuss the opportunities that exist at the interface of control theory, statistical inference, and neuroscience to devise a control-theoretic framework for BMI design and help develop the next-generation BMI control algorithms.

The design of Viterbi decoder for low power consumption space time trellis code without adder architecture using RTL model

Purpose This paper aims to describe the real-time design and implementation of a Space Time Trellis Code decoder using Altera Complex Programmable Logic Devices (CPLD). Design/methodology/approach The code uses a generator matrix designed for four-state space time trellis code (STTC) that uses quadrature phase shift keying (QPSK) modulation scheme. The decoding process has been carried out using maximum likelihood sequences estimation through the Viterbi algorithm. Findings The results showed that the STTC decoder can successfully decipher the encoded symbols from the STTC encoder and can fully recover the original data. The data rate of the decoder is 50 Mbps. Originality/value It has been shown that 96 per cent improvement of the total logic elements in Max V CPLD is used compared to the previous literature review.

A Hardware Decoder Architecture for General String Matching Technique

This paper proposes a low cost hardware decoder design and architecture that supports general string matching (SM) using both a primary reference buffer (PRB) and a secondary reference buffer (SRB). An SM decoding module mainly performs string copy operation. The SM decoding module can also support intra block copy and palette decoding because both are actually two special cases of general string copy. The proposed architecture has four pipeline stages. The theoretical lowest system clock frequency required to guarantee worst case string copy operation using single-port SRAM is lower than the video output pixel rate, which is the product of frame resolution and frame rate. The design uses four pieces of SRAMs with size of 24K bytes, 16.5K bytes, 4K bytes, and 3K bytes, respectively. The first one is specific to SM and the other three are shared by traditional hybrid decoding operations. The SM decoding module has 69.5K logic gate count and can achieve 60 fps real time SM decoding for 4K ( $4096\times 2160$ ) video at 218 MHz working frequency.

Non-binary LDPC Decoder Design over Rayleigh Channel for FPGA Implementation

Non-binary LDPC Decoder Design over Rayleigh Channel for FPGA Implementation

Feedback control policies employed by people using intracortical brain–computer interfaces

Objective. When using an intracortical BCI (iBCI), users modulate their neural population activity to move an effector towards a target, stop accurately, and correct for movement errors. We call the rules that govern this modulation a ‘feedback control policy’. A better understanding of these policies may inform the design of higher-performing neural decoders. Approach. We studied how three participants in the BrainGate2 pilot clinical trial used an iBCI to control a cursor in a 2D target acquisition task. Participants used a velocity decoder with exponential smoothing dynamics. Through offline analyses, we characterized the users’ feedback control policies by modeling their neural activity as a function of cursor state and target position. We also tested whether users could adapt their policy to different decoder dynamics by varying the gain (speed scaling) and temporal smoothing parameters of the iBCI. Main results. We demonstrate that control policy assumptions made in previous studies do not fully describe the policies of our participants. To account for these discrepancies, we propose a new model that captures (1) how the user’s neural population activity gradually declines as the cursor approaches the target from afar, then decreases more sharply as the cursor comes into contact with the target, (2) how the user makes constant feedback corrections even when the cursor is on top of the target, and (3) how the user actively accounts for the cursor’s current velocity to avoid overshooting the target. Further, we show that users can adapt their control policy to decoder dynamics by attenuating neural modulation when the cursor gain is high and by damping the cursor velocity more strongly when the smoothing dynamics are high. Significance. Our control policy model may help to build better decoders, understand how neural activity varies during active iBCI control, and produce better simulations of closed-loop iBCI movements.

Single-Tap Precoders and Decoders for Multiuser MIMO FBMC-OQAM Under Strong Channel Frequency Selectivity

The design of linear precoders or decoders for multiuser (MU) multiple-input multiple-output (MIMO) filterbank multicarrier (FBMC) modulations in the case of strong channel frequency selectivity is presented. The users and the base station (BS) communicate using space division multiple access (SDMA). The low complexity proposed solution is based on a single tap per-subcarrier precoding/decoding matrix at the base station (BS) in the downlink/uplink. As opposed to classical approaches that assume flat channel frequency selectivity at the subcarrier level, the BS does not make this assumption and takes into account the distortion caused by channel frequency selectivity. The expression of the FBMC asymptotic mean squared error (MSE) in the case of strong channel selectivity derived in earlier works is developed and extended. The linear precoders and decoders are found by optimizing the MSE formula under two design criteria, namely zero forcing (ZF) or minimum mean squared error (MMSE). Finally, simulation results demonstrate the performance of the optimized design. As long as the number of BS antennas is larger than the number of users, it is shown that those extra degrees of freedom can be used to compensate for the channel frequency selectivity.

Design and Implementation of Operation-Reduced LDPC Decoder Based on a Check Node Stopping Scheme

In this paper, we propose an operation-reduced low-density parity check (LDPC) decoder design and implementation by stopping reliable operation of check nodes of the iterative two-phase message passing (TPMP) min-sum algorithm (MSA). A check node stopping (CNS) scheme is used to tag reliability of check nodes by detecting the magnitudes of the check node belief messages with a threshold. The operation of reliable check nodes tagged by the CNS scheme can be stopped in the later iterations. The proposed LDPC decoder that employs the CNS scheme can significantly terminate the redundant operations of check nodes and efficiently reduce the power consumption of decoder. From the simulations under WiMAX QC LDPC decoding with high channel quality, the CNS scheme achieves up to 12% stopping rate of check nodes with a loss of coding gain less than 0.1 dB. The WiMAX QC LDPC decoder chip that employs the CNS scheme is implemented by a 90-nm CMOS process. Compared with the LDPC decoder that employs no CNS scheme, the overall power dissipation of the proposed LDPC decoder is decreased by 4.1% with 0.5% area overhead.

Individual Channel Estimation for AF-Based Relaying Systems Using In-Band Pilots

In amplify and forward cooperative relaying system, the knowledge of individual channel state information (CSI) is essential for coherent decoding and optimal design. To assist in the estimation of the individual channels, we proposed an in-band pilot strategy, where some cooperative data at the relay are discarded to insert pilots that can be utilized to estimate the relay to destination link. The new cooperative strategy implies that relay not only helps the source to transmit cooperative data, meanwhile, assisting the destination to acquire the individual CSI at the cost of cooperative information. Although some useful data are lost due to insertion of in-band pilots, the detection performance can be maintained with a simple iterative reconstruction method. Furthermore, if the direct link is available, the received signals from both the source and the relay can be combined to achieve spatial diversity. Simulation results are presented to assess the performance of the proposed schemes.

High-Accuracy Compressed Sensing Decoder Based on Adaptive <inline-formula> <tex-math notation="LaTeX">$(\ell_{0},\ell_{1})$</tex-math> </inline-formula> Complex Approximate Message Passing: Cross-layer Design

Compressed sensing (CS) allows a signal that is sparse in certain domain to be acquired and reconstructed accurately with only a small number of samples. In this paper, we propose an adaptive $(\ell_{0},\ell_{1})$ complex approximate message passing (CAMP) algorithm and its hardware implementation for complex-valued sparse signal recovery. Compared with the existing CAMP algorithm which solves $\ell_{1}$ -regularized least squares problems, our proposed algorithm adaptively switches between $\ell_{0}$ and $\ell_{1}$ -regularized least squares and therefore significantly outperforms the original CAMP. We implement the architecture in a medium-sized field-programmable gate array (FPGA) chip. For a sparse stepped frequency waveform radar application, we perform experiments on the simulated data and the data collected by a real radar system. According to the result, the decoder design achieves 7.2 dB improvement over the conventional CAMP architecture with less than 27.4% extra hardware cost.

Optimal Semiadaptive Transmission With Artificial-Noise-Aided Beamforming in MISO Wiretap Channels

This paper studies the design of artificial-noise-aided (AN-aided) secure transmission in slow-fading multiple-input–single-output (MISO) channels. We consider the scenario where a multiantenna transmitter sends messages to a single-antenna legitimate receiver in the presence of multiple noncolluding single-antenna eavesdroppers. It is assumed that the transmitter possesses instantaneous channel state information (CSI) of the legitimate channel but only the statistics of the eavesdropper's channels. Instead of adopting the well-known adaptive and nonadaptive transmission schemes, we consider the newly proposed semiadaptive scheme, in which the communication rate is fixed, and the secrecy rate is adaptively adjusted according to the legitimate channel's CSI. Compared with the adaptive scheme, a major advantage of fixing the communication rate is that the codebook can be fixed, and thus, the encoder and decoder designs are both simplified. We consider a generalized AN-aided beamforming structure, which allows arbitrary beamforming direction. Specifically, we focus on the problem of maximizing the secrecy throughput on the premise of reliable and secure transmission. By solving this problem, the optimal beamforming direction, power-allocation parameters, and secrecy rate are derived in closed form, and the optimal communication rate is obtained numerically. Finally, simulation results are presented to show the performance of the semiadaptive scheme.

Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SDBCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 ㏈ coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-㎚ CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.