Design Of Combinational Logic Circuits Research Articles

Teaching Design and Practice of "Three-wide Education" Integrating into Combinational Logic Circuit Design

This article explores the integration of "Three-Wide Education" into the course ‘Digital Electronic Technology’ with a specific focus on the content related to the design of combined logic circuits. As education continues to evolve, the goals of higher education have shifted from simply imparting knowledge to nurturing students' holistic development and actively engaging them in societal progress. In today's social context, the cultivation of high-caliber electronic information professionals with a strong sense of social responsibility has become a central objective of higher education. Consequently, curriculum-based "Three-Wide Education" has gained prominence as a pivotal component of higher education reform. Drawing upon the thematic elements of "Three-Wide Education" within the chapter on combinatorial logic circuit design, this article embarks on instructional design. The primary objective is to seamlessly integrate knowledge dissemination with value-based guidance through practical exercises in "Three-Wide Education" within the curriculum.

A GA Based Simple and Efficient Technique to Design Combinational Logic Circuits Using Universal Logic Modules

A Genetic Algorithm based optimization technique for the design of combinational logic circuits using Universal logic Modules, 2-1 multiplexer or 2-1 Reed Muller block is proposed. In contrast to applying same select signals for all the units in a level of tree network in conventional methods, the proposed method allows any variable to be used as select signal to any unit in any level. In addition to the use of variables as select signals, the proposed method uses functions derived from previous level as select signal which is not the case in conventional methods. With this technique, complexity of the circuits is made lesser which leads to lesser power consumption, area and delay as compared to the current and conventional methods available in the literature. Standard Boolean functions are implemented to design circuits up to six variables and the results are validated with benchmark functions.

A Simplified Efficient Technique for the Design of Combinational Logic Circuits

A Simplified Efficient Technique for the Design of Combinational Logic Circuits

Genetic Algorithm Based Design of Combinational Logic Circuits Using Universal Logic Modules

A new approach for the evolutionary design of combinational logic circuits using Genetic Algorithm and 2-1 multiplexers is presented. Binary multiplexer is the only design unit used. Repeated use of the same element reduces the manufacturing cost which is of prime importance in VLSI design. Any Boolean function can be realized using 2-1 multiplexers with this method. The performance of the circuits evolved was compared with standard implementation technique. Power, area, and delay involved were analyzed using Synopsys design compiler. With the proposed technique, the number of modules needed is reduced significantly, thereby reducing the power, area, cost and delay.

Virtual reconfigurable architecture for evolving combinational logic circuits

A virtual reconfigurable architecture (VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level. The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect (PCI) board with an Xilinx Virtex xcv2000E field programmable gate array (FPGA). To improve the quality of the evolved circuits, the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit. To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning, a self-adaptive mutation rate control (SAMRC) scheme is introduced. In the evolutionary process, the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations. The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function, a 2-bit multiplier, and a 3-bit multiplier. The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort, when compared to the existing evolvable hardware approaches.

Parallel genetic algorithm for solving the combinational logic circuit design problem on supercluster.

Parallel genetic algorithm for solving the combinational logic circuit design problem on supercluster.

A Discussion of the Design Method of Full Adder Circuit

A bit full adder is a very important component in the digital system. Design of a full-adder circuit, as an example, by changing its output function expression in the form of expression, use the gates, decoder, multiplexer etc 74 series devices, the eight circuits realization form are given respectively, and briefly analyzed the advantages and disadvantages of the various circuit implementation. The example show that the design of combinational logic circuits has mobility and variety, it could give the instructiveness and the guiding for other design of combinational logic circuits.

Evolutionary design of combinational circuit based on game genetic algorithm

To improve the speed and efficiency of combinational logic circuit design,this paper presented a Game Genetic Algorithm(GGA).In GGA,each output of the circuit was regarded as a player. The connection and combination of logic gates of each output were regarded as strategies.GGA transformed the circuit design problem to an optimal game decision-making one.The choice of policy was realized by genetic algorithm,and then the game model was built.Simulation results show that the method is effective.

K-maps: a vehicle to an optimal solution in combinational logic design problems using digital multiplexers

Application of Karnaugh maps (K-Maps) for the design of combinational logic circuits and sequential logic circuits is a subject that has been widely discussed. However, the use of K-Maps in the design of combinational logic circuits using medium scale integration (MSI) devices has not yet been widely explored. The techniques discussed in this paper, were devised, and implemented by the author as an attempt to resolve the problem of not having a criterion to determine an optimal design solution, when students presented several different designs. The devised method entails the designer to solve three distinct problems. First is an assignment problem, i.e. assigning input variables to select lines of the multiplexer. Each assignment results in a different assignment K-Map. Secondly, is a simplification problem i.e. finding the most simplified solution of each of the assignment maps. Lastly, is an optimization problem. Key Words: Karnaugh maps (K-Maps), combinational logic circuits, optimal design solution, multiplexer, simplified solution Botswana Journal of Technology Vol.13(2) 2004: 29-34

Design of combinational logic circuits through an evolutionary multiobjective optimization approach

In this paper, we propose a population-based evolutionary multiobjective optimization approach to design combinational circuits. Our results indicate that the proposed approach can significantly reduce the computational effort required by a genetic algorithm (GA) to design circuits at a gate level while generating equivalent or even better solutions (i.e., circuits with a lower number of gates) than a human designer or even other GAs. Several examples taken from the literature are used to evaluate the performance of the proposed approach.

Towards automated evolutionary design of combinational circuits

In this paper, we propose a methodology based on a genetic algorithm (GA) to automate the design of combinational logic circuits in which we aim to minimize the total number of gates used. Our results are compared against those produced by human designers and by another GA-based approach. We also analyze the importance of using a non-binary representation in this problem despite the commonly accepted notion of universality of the binary representation in all kinds of GA-based applications.

Design of robustly testable combinational logic circuits

An integrated approach to the design of combinational logic circuits in which all path delay faults and multiple line stuck-at, transistor stuck-open faults are detectable by robust tests is proposed. Robustly testable static CMOS primitive logic circuit designs are presented for any arbitrary combinational logic function. They require no special gates, and fan-in and fan-out constraints do not affect the designs. Extra controllable inputs or additional hardware to achieve testability was not used. It is demonstrated that the method guarantees the design of CMOS logic circuits in which all path delay faults are locatable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Combinational Circuit Synthesis with Time and Component Bounds

New results are given concerning the design of combinational logic circuits. We give time and component bounds for combinational circuits specified in several ways. For any sequential machine defined by linear recurrence relations, we discuss an algorithm for the synthesis of equivalent combinational logic. The procedure includes upper bounds on the time and components involved. We also discuss the transformation of nonlinear recurrences into combinational circuits. Examples are given using gates as well as IC's as components. These include binary addition, multiplication, and ones' position counting. The time and component bounds our procedure yields compare favorably with traditional results.

On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests

This paper considers the design of combinational logic circuits which require a minimal or near-minimal number of tests. Bounds on the number of tests required by various network structures are considered. It is shown that for an n-input fanout-free network, the number of single and multiple fault detection test lies between 2 √n and n + 1, while the number of fault locations tests lies between 2 √n and 2n.