Design Of Clock Distribution Networks Research Articles

QuCTS—Single-Flux Quantum Clock Tree Synthesis

Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS—single-flux Quantum (SFQ) Clock Tree Synthesis—is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time.

Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation

Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation

Power Efficient 3D Clock Distribution Network Design with TSV Count Optimization

This paper mainly focuses on power efficient and low skew clock network design for three-dimensional ICs based on through- silicon via (TSV). Clock tree synthesis is carried out in two major steps; 1) 3D Abstract clock tree generation; 2) buffering with skew and slew consideration. Firstly we design abstract clock tree by using(3D-MMM) followed by skew and slew aware buffer insertion. We analyze how the inclusion of TSVs will affect RC parasitic of an otherwise 2D clock network design by studying Elmore Delay model for 3D topology. We propose extension to the Exact Zero Skew (EEZE- Extended Exact Zero Skew) algo- rithm by Dr. Tsay for 3D topology which considers TSV resistance-capacitance. This algorithm designs the clock tree by using optimum number of TSVs suitable for the circuit. This is accomplished by merging cost comparison between sets obtained after 3D MMM implementation. This showed 19% to 23% reduction in wire-length. Spice analysis of the obtained clock network resulted in 16% to 18% reduction in clock power dissipation. This indicates that, 1) With optimum TSV count, wire-length of the clock tree reduces by the considerable amount, 2) Small trade-off between optimal TSV count and wire-length, reduces power dissipation.

ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

This paper presents a topology-based solution for a low-skew rotary oscillator array (ROA) clock distribution network design. An ROA-brick structure is proposed that limits the traveling wave oscillation to only two uniform ring rotation directions in the ROA-brick: all the rings in clockwise (CW) direction or all the rings in counter CW direction. An ROA built from the ROA-bricks has the following advantages: 1) similar to the ROA-brick, only two uniform ring rotation directions are feasible in the ROA; 2) the same phase tapping points of all the rings in the ROA are identifiable; and 3) these same phase tapping points of the ROA are independent from the two possible rotation directions. It is mathematically proved that the ROA-brick is the only ROA structure, which can limit the ring rotation direction combinations so as to guarantee the generation of same phase clock signals. The proposed brick-based ROA clock generation and distribution networks are designed for ISPD 10 clock benchmarks demonstrating the gigahertz operation with the low-skew clock generation and distributions through HSPICE.

A TVC based Clock Fault Detection Circuit for Modern Clock Distribution Network

Modern clock distribution design continues to face challenges in spite of significant advances in the last decade. Clock fault has become a problem in clock distribution network (CDN) in recent years as clock frequency is more than 1GHz now. In this paper, we propose a time-to-voltage converter (TVC) based on-line clock fault detect circuit to enhance flexibility and reliability in design of CDN, which only consists of twelve transistors and two minor capacitors. The proposed circuit transforms the clock fault to deviation of voltage (TVC) but without constant current source and analog-to-digital converter (ADC). Simulation-based results show that the proposed circuit can enhance the reliability of clock distribution network and detect clock jitter fault on-chip as high as 1GHz.

Automation of clock distribution network design for digital integrated circuits using divide and conquer technique

One of the most carefully engineered components of a digital integrated circuit is the clock distribution network. A clock is unarguably the most important signal and the network used for its distribution contributes to nearly half of the entire power dissipated by the IC. The design of a clock distribution network requires tremendous resources in terms of time and effort to achieve optimized results. This paper discusses the development of a new algorithm with smaller time complexity for automation of the design of clock distribution network that can greatly reduce the time and effort required, at the same time meeting the conditions set for delays and maximum allowable power dissipation.

Clock distribution networks in synchronous digital integrated circuits

Clock distribution networks synchronize the flow of data signals among synchronous data paths. The design of these networks can dramatically affect system-wide performance and reliability. A theoretical background of clock skew is provided in order to better understand how clock distribution networks interact with data paths. Minimum and maximum timing constraints are developed from the relative timing between the localized clock skew and the data paths. These constraint relationships are reviewed, and compensating design techniques are discussed. The field of clock distribution network design and analysis can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom digital integrated circuits; 2) the automated layout and synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the scheduling of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described the clock distribution networks of specific industrial circuits are surveyed and future trends are discussed.

High Performance Clock Distribution Networks

As semiconductor technologies operate at increasingly higher speeds, system performance has become limited not by the delays of the individual logic elements and interconnect but by the ability to synchronize the flow of the data signals. Different synchronization strategies have been considered, ranging from completely asynchronous to fully synchronous. However, the dominant synchronization strategy within industry will continue to be fully synchronous clocked systems. Systems ranging in size from medium scale circuits to large multimillion transistor microprocessors and ultra-high speed supercomputers utilize fully synchronous operation which require high speed and highly reliable clock distribution networks. Distributing the clock signals within these high complexity, high speed processors is one of the primary limitations to building high performance synchronous digital systems. Greater attention is therefore being placed on the design of clock distribution networks for large VLSI-based systems.

Clock Distribution Methodology for PowerPC™Microprocessors

Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems.