Clock Distribution Methodology for PowerPC™Microprocessors

Abstract

Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPC™ microprocessors that aim at alleviating some of these problems.