H-Tree Clock Synthesis in RSFQ Circuits

Abstract

Rapid single flux quantum (RSFQ) technology promises high performance, energy efficient supercomputers to achieve DoE exascale computing. An important challenge in VLSI complexity RSFQ circuits is ultra-high speed clocking and synchronization. A methodology to support the automated design of clock distribution networks for SFQ circuits is the focus of this paper. Global clock synthesis of SFQ circuits is applied to produce a near zero skew clock network. An algorithm is presented that produces an SFQ H-tree network with asymmetric leaves to propagate the clock signal to all SFQ gates. A Python-based system with location information for the interconnects, splitters, and leaves is described. The algorithm determines the physical locations and connections within the SFQ clock network and is applicable to automated routing and clock tree synthesis.