Design Compiler Research Articles

Building a Graphical Modelling Language for Efficient Homomorphic Encryption Schema Configuration: HomoLang

Homomorphic encryption (HE) is an emerging technology that enables computing on data while the data is encrypted. It has advantages, but it also has a significant difficulty. Programmers that use General-Purpose Programming Languages (GPPLs) may find it difficult to handwrite the script code for the HE correctly. This paper presents the front-end compiler design for the first graphical modelling language (DSML) to implement HE schemas, called HomoLang. It is providing a graphical environment with graphical building nodes that represent the HE concepts to enable the building of HE schemas. A high degree of abstraction and a decrease in grammatical and runtime errors improved the expressiveness and efficiency of implementation. Six security tests for security analysis were provided. The efficiency of the submitted language was evaluated using four subjective metrics. This paper provides a detailed explanation of the attributes, evaluation details, and design of the submitted HomoLang.

генезис дизайн-аукционов в интернет-рекламе

The article is devoted to the genesis of design auctions, as well as their main tool, sponsored listing in online advertising, which is the most marginal option for capitalization of online marketing resources with a yield approaching a trillion dollars. The purpose of the study was to study the genesis of online advertising, this trend and the content of its development. The tasks, historical stages and key features of the development of “sponsored listings” tools, which stand out non-trivially and are leading in the online advertising marketing market in direct relation to the user’s current online activity, are identified. The final results of the study substantiate the importance of the compilation of Game Theory and auction design, the logical consequence of the synergy of which was the direct development of unique sponsored listing tools. The research is based on the analysis of foreign and Russian publications, as well as on the statistical conclusions of marketing data.

Expanding hardware accelerator system design space exploration with gem5-SALAMv2

With the prevalence of hardware accelerators as an integral part of the modern systems on chip (SoCs), the ability to model accelerators quickly and accurately within the system in which it operates is critical. This paper presents gem5-SALAMv2 as a novel system architecture for LLVM-based modeling and simulation of custom hardware accelerators integrated into the gem5 framework. It overcomes the inherent limitations of state-of-the-art trace-based pre-register-transfer level (RTL) simulators by offering a truly “execute-in-execute” LLVM-based model. It enables scalable modeling of multiple dynamically interacting accelerators with full-system simulation support. To create long-term sustainable expansion compatible with the gem5 system framework, gem5-SALAM offers a general-purpose and modular communication interface and memory hierarchy integrated into the gem5 ecosystem, streamlining designing and modeling accelerators for new and emerging applications. gem5-SALAMv2 expands upon the framework established in gem5-SALAMv1 with improved LLVM-based elaboration and simulation, improved and more extensible system integration, and new automations to simplify rapid prototyping and design space exploration. 11Conference Paper Extension: This work extends the work presented in gem5-SALAM: A System Architecture for LLVM-based Accelerator Modeling from MICRO 2020 (Rogers et al., 2020). This work expands on the aforementioned work by revamping the gem5-SALAM internals to provide more robust and extensible simulations, introducing new automation tools for expanding and simplifying design space exploration, and demonstrates the new capabilities of gem5-SALAMv2 by exploring multiple configurations of simple neural network architectures.Validation on the MachSuite (Reagen et al., 2014) benchmarks presents a timing estimation error of less than 1% against the Vivado High-Level Synthesis (HLS) tool. Results also show less than a 4% area and power estimation error against Synopsys Design Compiler. Additionally, system validation against implementations on an Ultrascale+ ZCU102 shows an average end-to-end timing error of less than 2%. Lastly, we demonstrate the upgraded capabilities of gem5-SALAMv2 by exploring accelerator platforms for two deep neural networks, LeNet5 and MobileNetv2. In these explorations, we demonstrate how gem5-SALAMv2 can simulate such systems and guide architectural optimizations for these types of accelerator-rich architectures. 22The most up-to-date version of gem5-SALAMv2 is available at https://github.com/TeCSAR-UNCC/gem5-SALAM..

Efficient architecture for ocular artifacts removal from EEG: A Novel approach based on DWT-LMM

Medical practitioners use portable electroencephalogram (EEG) headset to identify Neuro Developmental Disorders (NDD). However, the analysis of EEG signals gets affected as the recorded electrical activity always contaminated with artifacts. A portable EEG headset requires area-efficient hardware and an effective method to remove ocular artifacts. In this paper, a method is proposed, which removes ocular artifacts efficiently and consumes less hardware. This proposed method involves determining the appropriate decomposition level to obtain approximation coefficients (ACs) and detail coefficients (DCs) for minimal loss of useful information present in the EEG signal. In addition, an algorithm is also proposed to perform wavelet thresholding on wavelet coefficients using Local Maximal and Minimal (LMM) to remove artifacts from EEG signals without disturbing the information related to brain activity. The functionality of the proposed method is verified using MATLAB R2021a tool by computing average correlation coefficient & RMSE performance metrics and the proposed method is also modeled using Verilog HDL. The results show that the proposed DWT-LMM approach had superior performance in removing artifacts from EEG signals with the average correlation coefficient and RMSE values of 0.9369 and 2.2252, respectively. The functionality of this HDL netlist is verified by the VCS simulator and synthesized by Synopsys design compiler 32 nm UMC library cells. The proposed architecture layout is generated after placement & routing using Synopsys IC Compiler tool by employing 32 nm cell libraries and the results shows that the layout consumes 6490.07 μm2 of area and 792.18 μw of power with supply voltage of 0.95 V. Hence, the proposed ocular artifacts removal method and architecture can be employed in portable/wearable brain-computer interface (BCI) devices.

New paradigms of water‐enabled electrical energy generation

AbstractNanotechnology‐inspired small‐sized water‐enabled electricity generation (WEG) has sparked widespread research interest, especially when applied as an electricity source for off‐grid low‐power electronic equipment and systems. Currently, WEG encompasses a wide range of physical phenomena, generator structures, and power generation environments. However, a systematic framework to clearly describe the connections and differences between these technologies is unavailable. In this review, a comprehensive overview of generator technologies and the typical mechanisms for harvesting water energy is provided. Considering the different roles of water in WEG processes, the related technologies are presented as two different scenarios. Moreover, a detailed analysis of the electrical potential formation in each WEG process is presented, and their similarities and differences are elucidated. Furthermore, a comprehensive compilation of advanced generator architectures and system designs based on hydrological cycle processes is presented, along with their respective energy efficiencies. These nanotechnology‐inspired small‐sized WEG devices show considerable potential for applications in the Internet of Things ecosystem (i.e., microelectronic devices, integrated circuits, and smart clothing). Finally, the prospects and future challenges of WEG devices are also summarized.

Homeostasis: Design and Implementation of a Self-Stabilizing Compiler

Mainstream compilers perform a multitude of analyses and optimizations on the given input program. Each analysis (such as points-to analysis) may generate a program-abstraction (such as points-to graph). Each optimization is typically composed of multiple alternating phases of inspection of such program-abstractions and transformations of the program. Upon transformation of a program, the program-abstractions generated by various analyses may become inconsistent with the modified program. Consequently, the correctness of the downstream inspection (and consequent transformation) phases cannot be ensured until the relevant program-abstractions are stabilized ; that is, the program-abstractions are either invalidated or made consistent with the modified program. In general, the existing compiler frameworks do not perform automated stabilization of the program-abstractions and instead leave it to the compiler pass writers to deal with the complex task of identifying the relevant program-abstractions to be stabilized, the points where the stabilization is to be performed, and the exact procedure of stabilization. In this article, we address these challenges by providing the design and implementation of a novel compiler-design framework called Homeostasis . Homeostasis automatically captures all the program changes performed by each transformation phase, and later, triggers the required stabilization using the captured information, if needed. We also provide a formal description of Homeostasis and a correctness proof thereof. To assess the feasibility of using Homeostasis in compilers of parallel programs, we have implemented our proposed idea in IMOP, a compiler framework for OpenMP C programs. Furthermore, to illustrate the benefits of using Homeostasis , we have implemented a set of standard data-flow passes, and a set of involved optimizations that are used to remove redundant barriers in OpenMP C programs. Implementations of none of these optimizations in IMOP required any additional lines of code for stabilization of the program-abstractions. We present an evaluation in the context of these optimizations and analyses, which demonstrates that Homeostasis is efficient and easy to use.

Biology System Description Language (BiSDL): a modeling language for the design of multicellular synthetic biological systems

BackgroundThe Biology System Description Language (BiSDL) is an accessible, easy-to-use computational language for multicellular synthetic biology. It allows synthetic biologists to represent spatiality and multi-level cellular dynamics inherent to multicellular designs, filling a gap in the state of the art. Developed for designing and simulating spatial, multicellular synthetic biological systems, BiSDL integrates high-level conceptual design with detailed low-level modeling, fostering collaboration in the Design-Build-Test-Learn cycle. BiSDL descriptions directly compile into Nets-Within-Nets (NWNs) models, offering a unique approach to spatial and hierarchical modeling in biological systems.ResultsBiSDL’s effectiveness is showcased through three case studies on complex multicellular systems: a bacterial consortium, a synthetic morphogen system and a conjugative plasmid transfer process. These studies highlight the BiSDL proficiency in representing spatial interactions and multi-level cellular dynamics. The language facilitates the compilation of conceptual designs into detailed, simulatable models, leveraging the NWNs formalism. This enables intuitive modeling of complex biological systems, making advanced computational tools more accessible to a broader range of researchers.ConclusionsBiSDL represents a significant step forward in computational languages for synthetic biology, providing a sophisticated yet user-friendly tool for designing and simulating complex biological systems with an emphasis on spatiality and cellular dynamics. Its introduction has the potential to transform research and development in synthetic biology, allowing for deeper insights and novel applications in understanding and manipulating multicellular systems.

Instruction Level Parallelism and Memory Synchronization

The simultaneous or parallel execution of a series of instructions within a computer program is known as instruction-level parallelism, or ILP. ILP stands for the average number of instructions executed throughout each stage of this parallel execution, to be more precise. The architecture known as instruction level parallelism (ILP) allows for the execution of several operations in parallel within a single process, each with its own set of resources, including address space, registers, identifiers, state, and program counters. It describes compiler design strategies and processors intended to carry out operations in parallel to increase processor performance, such as memory load and store, integer addition, and float multiplication.

Edge-sorter: A hardware sorting engine for area & power constrained edge computing devices

In recent years, hardware sorters have been an attracted topic for researchers. Since hardware sorters play a crucial role in embedded systems, several attempts have been made to efficiently design and implement these sorters. Previous state-of-the-art hardware sorters are not suitable for embedded edge computing devices because they (1) consume high power, (2) occupy high area, (3) work for limited data-width numbers, (4) require many memory resources, and (5) finally, their architecture is not scalable with the number of input records. This paper proposes a hardware sorter for edge devices with limited hardware resources. The proposed hardware sorter, called Edge-Sorter, processes 4 bits of input records at each clock cycle. Edge-Sorter utilizes the unary processing in its main processing core. Edge-Sorter has valuable attributes compared to previous state-of-the-art techniques, including low power consumption, low area occupation, sorting numbers without storing their indices, sorting numbers with arbitrary data-width, and scalable with the number of input records. The proposed approach is evaluated and compared with previous state-of-the-art techniques with two different implementation and synthesis environments: Xilinx Vivado FPGA-based and Synopsys Design Compiler 45-nm ASIC-based. The Synthesis results of both environments indicate that both Edge-Sorter techniques reduces area and power consumption on average by 80% and 90%, respectively compared to previous techniques.

DRcipher: A pseudo-random dynamic round lightweight block cipher

The Internet of Things (IoT) has gained popularity in various fields, including components such as embedded devices and wireless sensors. However, ensuring the security of data transmission from these devices is of critical importance. In light of these challenges, a novel lightweight encryption method called DRcipher is proposed in this paper for resource-constrained IoT devices. DRcipher has a 64-bit block size and supports either 96-bit or 128-bit key sizes. In order to improve the security, DRcipher employs a pseudo-random number of encryption rounds determined by the primary key. DRcipher adopts the structure of Generalized Feistel Network (GFN) with 4 branches, and its round functions consist of F-function, FF-function and RP permutation components. In particular, there is a negative feedback mechanism between the FF-function and the overall round of encryption functions. In addition, DRcipher is synthesised using Synopsys Design Compiler version A-2007.12-SP1 and the UMCL18G212T3 standard cell library. DRcipher-96 has an area footprint of 1546 Gate Equivalents (GE), while DRcipher-128 has a slightly larger area footprint of 1646 GE. Moreover, a comprehensive security analysis shows that the proposed DRcipher ensures high-level security redundancy against differential cryptanalysis, linear cryptanalysis, and so on.

Trustworthy Compiler Design for Generating Concrete Scenarios Toward Certifying Autonomous Driving Safety

Trustworthy Compiler Design for Generating Concrete Scenarios Toward Certifying Autonomous Driving Safety

Considerations on efficient lexical analysis in the context of compiler design

Each programming language needs a mechanism of translating source code into code understood by the computer, i.e., machine code or assembly. This is done by a compiler. A compiler is thus a fundamental tool for software development. Lexical analysis, as the first step of compilation, has an important role and should be performed in an optimal way. But not only compilers rely on lexical analysis. Its role lies nowadays also in pattern recognition or natural language processing. In this paper, we present some of the main aspects of lexical analysis and how to efficiently perform it. Our aim is to offer some guidelines in constructing a modern and efficient scanner (lexer), outlining the criteria, which should be considered, presenting some pitfalls, and comparing existent tools for compiler construction. The main contribution of the paper is to offer practical guidelines and recommendations, especially to graduate students and programmers, in constructing an efficient scanner (lexer), considering also the proper tools currently available.

Efficient approximate multipliers utilizing compact and low-power compressors for error-resilient applications

Approximate computing is one of the promising techniques in error-resilient applications to overcome high-density integration challenges, such as energy consumption and performance. Multipliers constitute a significant portion of computer arithmetic units, leading to considerable energy and time consumption. In this paper, we propose low-power and compact approximate compressors for composing approximate Dadda multiplier structures, including compressors, half adders, and full adders, which utilize three-phase partial product compression: truncated, approximation, and exact columns. In approximate columns, we consider approximate compressors derived from the truth table of the exact 4:2 compressor and simplified K-map entries based on the probability of each combination of inputs. An error-correcting module (ECM) is designed to distinguish specific cases and reduce the error metrics. All circuits were simulated using ModelSim and then synthesized using Design Compiler with the 15 nm FinFET technology. When compared to state-of-the-art works, our multipliers exhibit approximately 30%, 43%, and 10% reductions in power, area, and delay, respectively. To evaluate their functionality, we conducted image multiplication and implemented a simple multi-layer perceptron (MLP) neural network using the modified National Institute of Standards and Technology (MNIST) dataset in MATLAB with 0.998 mean structural similarity index metric (MSSIM), 51 dB peak-signal noise ratio (PSNR), and 95% classification accuracy.

OpenVCAD: An open source volumetric multi-material geometry compiler

Modern additive manufacturing has made significant advancements in multi-material fabrication techniques that allow for position-specific control of material deposition. With these advancements, design tools have fallen behind machine capabilities in specifying volumetric information. Traditionally, design and fabrication workflows have expressed multi-material objects as several single-material bodies. By storing only the information about the surfaces of the geometries, information about the volumetric composition of the solids is unrepresented. The intense interest in compliant mechanisms and meta-materials demands a new design method that can support architecting material distribution throughout an object. To address these needs, we present OpenVCAD, an open-source volumetric design compiler with multi-material capabilities. OpenVCAD provides a scriptable suite of geometric and material design methods that enable efficient representation of objects with complex geometry and material distributions. OpenVCAD allows functional specification of multi-material volumes that are parameterized on spatial locations, yielding complex multi-material distributions that would be impossible to describe using alternative methods. This paper will present the OpenVCAD pipeline, compare it to related work, and demonstrate its use through the design and manufacturing of functionally graded multi-material components.

Efficient Compiler Design for a Geometric Shape Domain-Specific Language: Emphasizing Abstraction and Optimization Techniques

The research paper represents a novel approach to the design and optimization of a compiler for a domain-specific language (DSL) focused on geometric shape creation and manipulation. The primary objective is to develop a compiler capable of generating efficient machine code while offering users a high level of abstraction. The paper begins with an overview of DSLs and compilers, emphasizing their importance in software development. Next, it outlines the specific requirements of the geometric shape DSL and proposes a compiler design that addresses them. This innovative approach considers DSL's unique features, such as shape creation and manipulation, and aims to generate high-quality machine code. The paper also discusses optimization techniques to enhance the generated code's quality and performance, including loop unrolling and instruction scheduling. These optimizations are particularly suited to the DSL, which focuses on geometric shape creation and manipulation and are integral to achieving efficient machine code generation. In conclusion, the paper emphasizes the novelty of this approach to DSL compiler design and anticipates exciting results from testing the compiler developed for the geometric shape DSL.

A neural network based background calibration for pipelined‐SAR ADCs at low hardware cost

AbstractThis paper proposes a background calibration scheme for the pipelined‐Successive Approximation Register (SAR) Analog‐to‐Digital Converter (ADC) based on the neural network. Due to the non‐linear function fitting capability of the neural network, the linearity of the ADC is improved effectively. However, the hardware complexity of the neural network limits its application and promotion in ADC calibration. Hence, this paper also presents the optimization schemes, including the neuron‐based sharing neural network and the partially binarized with fixed neural network, in terms of calibration architecture and algorithm. A 60 MS/s 14‐bit pipelined‐SAR ADC prototyped in 28‐nm technology is utilized to verify the feasibility of the proposed calibration method. The measurement results show that the proposed calibration greatly enhances the Spurious Free Dynamic Range (SFDR) and Signal‐to‐Noise‐and‐Distortion Ratio (SNDR) from low frequency to Nyquist frequency. Meanwhile, the original calibrator and improved calibrator are synthesized in Synopsys Design Compiler to compare their hardware complexity. Compared with the unoptimized version, the optimized schemes can decrease the logic area and the network weights up to 76% and 52%, with negligible loss in calibration performance.

Design of Complex Multiplier Using Vedic Mathematics

In this project, a 4x4 multiplier is implemented that utilizes the Urdhava Tiryakbhyam sutra method in Vedic mathematics. This method is applicable in all two decimal number multiplications which offers high speed calculation and improved efficiency. Thus, the design of a 4x4 Vedic-based multiplier is solely aimed at performing faster multiplications and achieving quicker processing speeds than the traditional multipliers. The architecture of the Vedic multiplier consists of four 2x2 multipliers and three adders of different bit sizes that are assembled using the Wallace tree implementation. The coding for the multipliers and adders is written in Verilog Hardware Description Language (HDL) in the Quartus Prime 17 Software. Functional simulation is then carried out to ensure that the Vedic multiplier performs the accurate multiplication operations, while the Verilog Compiled Simulator is employed to compile and simulate the multiplier design. Following this, the Design Compiler (DC) and Integrated Circuit Compiler (ICC) command scripts are then composed to allow the logic and physical synthesis to be performed on the Vedic and traditional multipliers. From there, the performance level of both these multipliers are assessed through reference to several key parameters such as timing, area, power consumption, overflow percentage and congestion statistics. Based on the results obtained in the synthesis process, the Vedic multiplier possesses faster operational speed than the traditional multiplier (due to a shorter processing time), butultimately exhibits a greater power consumption and wider area coverage.

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

Design and evaluation of ultra‐fast 8‐bit approximate multipliers using novel multicolumn inexact compressors

SummaryA multiplier, as a key component in many different applications, is a time‐consuming, energy‐intensive computation block. Approximate computing is a practical design paradigm that attempts to improve hardware efficacy while keeping computation quality satisfactory. A novel multicolumn 3,3:2 inexact compressor is presented in this paper. It takes three partial products from two adjacent columns each for rapid partial product reduction. The proposed inexact compressor and its derivatives enable us to design a high‐speed approximate multiplier. Then, another ultra‐fast, high‐efficient approximate multiplier is achieved by utilizing a systematic truncation strategy. The proposed multipliers accumulate partial products in only two stages, one fewer stage than other approximate multipliers in the literature. Implementation results by the Synopsys Design Compiler and 45 nm technology node demonstrate nearly 11.11% higher speed for the second proposed design over the fastest existing approximate multiplier. Furthermore, the new approximate multipliers are applied to the image processing application of image sharpening, and their performance in this application is highly satisfactory. It is shown in this paper that the error pattern of an approximate multiplier, in addition to the mean error distance and error rate, has a direct effect on the outcomes of the image processing application.

System integration based on packing, piping and harness routing automation using graph-based design languages

The implementation of a fully instrumented, automated and simulation-enabled engineering software platform capable of automating the currently still manual model-based systems engineering (MBSE) design process for physical systems architecture generation and optimization in an aircraft wing is presented. The software platform uses graph-based design languages to integrate and entirely automate the mainly manual packing, piping and harness routing design. This design automation and optimization is achieved by a novel software stack of an optimization software coupled with a design compiler. It is shown that through rule-based model generation by a design compiler in the form of a design graph as a central data model, a cross-domain data consistency is achieved. This allows for automated execution and coupling of engineering tasks over several different domains such as packing, piping and routing design to converge to an optimized wing physical architecture design variant in agreement with given predetermined design constraints.