Design Compiler Research Articles

Compiler for Detection of Program Vulnerabilities

Program Vulnerabilities may be unwarranted for any organization and may lead to severe system failure. Due to the advancement of technology there has been increase in the area of vulnerability attacks which are exploited by hackers for getting access to the system or insertion of their malicious code. In this paper we present a proposal for compiler design which prevents some common vulnerability. The output result for our compiler would be compile time warning stating the possible vulnerability in the code. We will also look into the details about the different type of vulnerability and how the attacker can exploit those vulnerabilities in order to corrupt the system. The knowledge of various vulnerability creation areas have been used to design a compiler for vulnerability prevention. Compiler in this publication uses the symbol table generation mechanism for syntactically, semantically segregation of executable code and canary guard mechanism for the protection of cases of buffer overflow. Major work in this area deals with the simple scenarios for vulnerability detection but our aim is to check for various complicated scenarios and non common possibilities for program attack and designing a framework preventing such kinds of attacks. General Terms Lexical Analysis, Syntax Analysis, Parser, Token, Semantic Analyzer, Symbol table, Random XOR.

VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

In this paper, hardware efficient truncated multiplier using modified booth algorithm is proposed for signed bit multiplication, such that the average absolute error is kept minimum. The proposed methodology truncates the least significant bits (LSBs) of the final product and thus minimizes the number of full adders and half adders used in partial product accumulation. This we achieve by non-generation of an initial partial product and deletion of certain LSBs in higher order partial products. To minimize the error due to non generation and omission, we add compensation bits at appropriate retained bit positions. Experimental analysis of the proposed truncation algorithm implemented in modified booth encoded multiplier using Synopsys design compiler demonstrates area saving of nearly 25.1 % for an 8 × 8 design. The functionality of the proposed design is verified by implementing in a signal processing system.

High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications

prolific use of images & videos in portable devices, raised the need to develop the efficient architectures for the ever increasing demand of portability with low power and high performance quality metrics. However the images and videos are the information's to be stored, but there compression while storing is the important part. This paper introduces a basic hardware component for the compression architectures. Comparator augments as general purpose core to Sum of Absolute difference (SAD) architecture used for the object recognition, generation of disparity maps of the stereo images and for estimating the motion in videos. The Subtraction part of the comparator is optimized by providing the parallel computation in processing the 2's complement operation. Transistor stacking and Logic optimization concepts are utilized to reduce the leakage power of the comparator design. 4-bit wide Comparator with smallest of two binary numbers functionality is modeled using Verilog HDL and synthesized using Synopsys Design Compiler. The design was mapped to 65nm technological library node and results were benchmarked with respect to standard ASIC design methodology. The proposed architectures have resulted in reduced leakage power about 7- 42 % for different proposed architectures and enabled the different corners for analysis.

Reconfigurable Adder Architectures for Low Power Applications

The growing design complexity has attracted the designs with Reconfigurable fabrics, where adaptable fabrics are utilized to solve the computational problems. Reconfigurable computing provides the flexibility in arriving at the problem specific architectures which helps in improving the performance due to custom approach. In this paper, a flexible reconfigurable architecture with different adder variants like Ripple Carry, Carry Look-ahead, Carry Select and Carry Bypass adders are implemented to form dynamically reconfigurable Hybrid adder architectures. Such hybrid architectures are utilized for the applications where design constraints are only for low power or high performance or the low area or sometimes a balanced design metrics. The design was modelled using Verilog HDL and synthesized in Synopsys Design Compiler by mapping to TSMC 65nm technology node. Standard ASIC design methodologies are considered to bench mark the results. The proposed architecture enables the designer to perform efficient Design Space Exploration. The design can be made adaptable to any of the reconfigurable processor and a similar improvement can be obtained. The proposed architectures results in 18-54% reduced power consumption when designed with various combinations of reconfigurable adder architectures and also accounted for 14-44% of area reduction.

Low-Area Wallace Multiplier

Multiplication is one of the most commonly used operations in the arithmetic. Multipliers based on Wallace reduction tree provide an area-efficient strategy for high speed multiplication. A number of modifications are proposed in the literature to optimize the area of the Wallace multiplier. This paper proposed a reduced-area Wallace multiplier without compromising on the speed of the original Wallace multiplier. Designs are synthesized using Synopsys Design Compiler in 90 nm process technology. Synthesis results show that the proposed multiplier has the lowest area as compared to other tree-based multipliers. The speed of the proposed and reference multipliers is almost the same.

Compiler Construction for a Network Identification

The Compiler Construction is mainly used to improve the network processing system through the advance advance compiler design.The name Compiler is primarily used for programs that translate source code from a high –level programming language to a lower level language.The advance compiler design is useful in the industrial application like telecommunication. Our approach to increase the flexibility ,productivity and usability of the system to target with the minimal effort .we use the bit level addressing for the network processor we show how a compiler backend has been design and also improve the feature of the compiler and fully operational. A compiler is a computer program (or set of programs) that transforms source code written in a programming language (the source language) into another computer language (the target language, often having a binary form known as object code The most common reason for wanting to transform source code is to create an executabe program.

Design of write merging and read prefetching buffer in DRAM controller for embedded processor

Write merging and read prefetching are effective methods for improving processor performance, and they are mainly used in processors for desktop or server. As embedded system requires more powerful microprocessor, how to improve the performance of embedded processor is worthy of concern. This paper presents the architecture of write merging and read prefetching buffer in DRAM controller for embedded processor. The evaluation model is constructed, and the result demonstrates that the proposed method can reduce cache miss penalty dramatically. Additionally, the design of DRAM controller with write merging and read prefetching buffer is implemented and verified on FPGA platform, it can reduce CPI by 19.6% on average. Moreover, the RTL module of presented design is synthesized by Design Compiler, and synthesis result shows that hardware cost of proposed architecture is relatively small compared to performance amelioration.

Implementation of Shock Filter for Digital X-Ray Image Processing

X-ray image might be corrupted by noise or blurring because of signal transmission or the bad X- ray lens. This paper presents a two-stage shock filter based on Partial Differential Equations (PDE) to restore noisy blurred X-ray image. Shock filters are popular morphological methods. They are used for noise removal, edge enhancement and image segmentation. Our experimental results show that the performances of shock filter are excellent in X-ray image. The peak signal-to-noise ratio (PSNR) values are 38 dB at least in restoring the noisy X-ray image. The sharpness of image’s edges increase in enhancing the blurred X-ray image. Furthermore, this paper proposes a VLSI architecture for accelerating the high-definition (HD) X-ray image (944 p) process. This paper implements the architecture in FPGA. The hardware cost is low because the computation of shock filter is low complex. To achieve the real-time processing specification, this paper uses a 5-series shock filter architecture to implement computation of HD X-ray image. This paper demonstrates a 944 p, 43.1-fps solution on 100 MHz with 133 k gate counts in Design Compiler, and with 2904 logic elements in FPGA.

Experimenting an implementation-focused approach to undergraduate compiler course

Compiler construction is one of the most challenging courses to teach in undergraduate computer science curriculum. In a traditional compiler course, many theoretical topics are covered and a compiler project is assigned. Our previous experience shows that this approach not only is challenging but also can be ineffective sometimes. To cover the extensive amount of material within a semester is a struggle. To expect students to produce a working compiler is also impractical since most undergraduates have little experience in developing large software. Our preliminary experiment using an implementation-focused approach produces many positive outcomes. In this approach, the lectures focused on the case study of the design and implementation of a Pascal compiler using a language independent framework. For the project, students successfully used the given language independent framework to design and develop a working compiler for a modified subset C language.

Low Power Adder Based Digital Filter for QRS Detector

Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

Low power adder based auditory filter architecture.

Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

Computing in Operations Research Using Julia

The state of numerical computing is currently characterized by a divide between highly efficient yet typically cumbersome low-level languages such as C, C++, and Fortran and highly expressive yet typically slow high-level languages such as Python and MATLAB. This paper explores how Julia, a modern programming language for numerical computing that claims to bridge this divide by incorporating recent advances in language and compiler design (such as just-in-time compilation), can be used for implementing software and algorithms fundamental to the field of operations research, with a focus on mathematical optimization. In particular, we demonstrate algebraic modeling for linear and nonlinear optimization and a partial implementation of a practical simplex code. Extensive cross-language benchmarks suggest that Julia is capable of obtaining state-of-the-art performance. Data, as supplemental material, are available at http://dx.doi.org/10.1287/ijoc.2014.0623 .

Combining intensification and diversification strategies in VNS. An application to the Vertex Separation problem

The Vertex Separation problem (VSP) is an NP-hard problem with practical applications in VLSI design, graph drawing and computer language compiler design. VSP belongs to a family of optimization problems in which the objective is to find the best separator of vertices or edges in a generic graph. In this paper, we propose different heuristic methods and embed them into a Variable Neighborhood Search scheme to solve this problem. More precisely, we propose (i) a constructive algorithm, (ii) four shake procedures, (iii) two neighborhood structures, (iv) efficient algorithmic strategies to explore them, (v) an extended version of the objective function to facilitate the search process and finally, (vi) we embed these strategies in a Reduced Variable Neighborhood Search (RVNS), a Variable Neighborhood Descent (VND) and a General Variable Neighborhood Search (GVNS). Additionally, we provide an extensive experimental comparison among them and with the best previous method of the literature. We consider three different benchmarks, totalizing 162 representative instances. The experimentation reveals that our best procedure (GVNS) improves the state of the art in both quality and computing time. This fact is confirmed by non-parametric statistical tests. In addition, when considering only the largest instances, the other two proposed variants (RVNS and VND) also obtain statistically significant differences with respect to the best previous method identified in the state of the art.

Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips

Network-on-chips (NoCs) have emerged as a scalable solution to the wire delay constraints, thereby providing a high-performance communication fabric for future multicores. Research has shown that power, area, and performance of the NoC architecture are tightly integrated with the design and optimization of the link, router (buffer and crossbar), and topology. Recent work has shown that adaptive channel buffers (on-link storage) can considerably reduce power consumption and area overhead by reducing or replacing the power-hungry router buffers. However, channel buffer design can lead to head-of-line (HoL) blocking, which eventually reduces the throughput of the network. In this paper, we design channel buffers and router crossbars to improve the performance (latency, throughput) while reducing the power consumption. In addition, we implement the proposed channel buffers and crossbar organizations in a concentrated torus (CTorus) topology which is a dual network without the additional area overhead. We compare other dual networks with leading topologies such as mesh2X, concentrated mesh2X (CMesh2X), and flattened butterfly2X (FBfly2X), each implemented with channel buffers. Our proposed designs analyze the power-performance-area tradeoff in designing channel buffers for NoC architectures while alleviating HoL blocking through buffer organizations and crossbar optimizations. Results using Synopsys design compiler showed that the buffer and crossbar organizations for an 8 × 8 mesh architecture can reduce power consumption by 25%-40%, improve throughput and reduce latency by 525%, while occupying 4%-13% more area when compared to the baseline architecture for both synthetic as well as real benchmark traces such as Princeton Application Repository for Shared-Memory Computers (PARSEC) and Standard Performance Evaluation Corporation (SPEC). CPU2006. When the energy-efficient buffer and crossbar organization was inserted into our CTorus topology, we further reduced energy dissipation by 32% and area by 53%, on average, over mesh2X, CMesh2X, and FBfly2X.

CROSS cyclic resource-constrained scheduling solver

Cyclic scheduling problems consist in ordering a set of activities executed indefinitely over time in a periodic fashion, subject to precedence and resource constraints. This class of problems has many applications in manufacturing, embedded systems and compiler design, production and chemical systems. This paper proposes a Constraint Programming approach for cyclic scheduling problems, based on modular arithmetic: in particular, we introduce a modular precedence constraint and a global cumulative constraint along with their filtering algorithms. We discuss two possible formulations. The first one (referred to as CROSS) models a pure cyclic scheduling problem and makes use of both our novel constraints. The second formulation (referred to as CROSS⁎) introduces a restrictive assumption to enable the use of classical resources constraints, but may incur a loss of solution quality. Many traditional approaches to cyclic scheduling operate by fixing the period value and then solving a linear problem in a generate-and-test fashion. Conversely, our technique is based on a non-linear model and tackles the problem as a whole: the period value is inferred from the scheduling decisions. Our approach has been tested on a number of non-trivial synthetic instances and on a set of realistic industrial instances. The method proved to effective in finding high quality solutions in a very short amount of time.

A Compiler Design Technique for Impulsive VDD Current Minimization

For electromagnet interference (EMI) optimization issues, different hardware-level techniques have been proposed. This paper focuses on an EMI optimization technique via a software-level technique. We propose a novel estimation and optimization tool for reducing conducted EMI at specified frequency by compiler technology. This study is not a research on compiler technique but an adaption of computer science-domain technology to EMI optimization research. The proposed tool can accept C language syntax and generate many versions of assembly programs. These assembly programs perform the same functionality defined by the input C program but with different conducted EMI behaviors when they are executed. The proposed tool can estimate, select, and generate the assembly program with the least amount of conducted EMI released during its execution. The experiment results show that the proposed tool can analyze test C-programs and generate lower EMI assembly programs. Currently, compared to a commercial compiler, the proposed technique can decrease conducted EMI by 2–5 dB at any specified frequency.

Burroughs Algol at Stanford University, 1960-1963

The decade between 1955 and 1965 brought a revolution to academic computing, both technologically and socially. As core memory replaced electrostatic memory while transistors replaced vacuum tubes, computers advanced from flakey and difficult-to-maintain devices to reliable appliances. At the same time (and partially as a consequence), the academic use of computing expanded rapidly, computing centers became increasingly essential facilities on every campus, and computer science began to gain acceptance as a legitimate academic discipline. This Anecdote recounts the author's experience during this dramatic shift in academic computing at Stanford University during the period between 1960 and 1963. It also records a chapter in the early development of compiler design and programming technology.

Design on Embedded Processor with Configurable Divider

By analyzing Cortex-M3 Instruction Set and AHB Bus protocol, a Cortex-M3 Instruction Set compatible 32-bit RISC embedded microprocessor with built-in an optimized 5+2-stage pipeline was realized in this paper. The performance of the 32-bit RISC processor is optimized by deepening pipeline and optimizing functional modules compared with Cortex-M3. According to division instructions, a configurable hardware divider in different realization ways was realized for different applications. The design of the system architecture was completed using Verilog hardware description language (Verilog HDL) and Top-down methodology. The logic function was corrected by VCS simulation FPGA verification. Design Compiler synthesis result shows that, the maximal dominant frequency of the RISC embedded microprocessor could be up to 95MHz with the 0.18um CMOS process of SMIC, and is improved by 31.94% compared with STM32 Cortex-M3 (72MHz).

CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis

Windowing techniques have been widely used for preprocessing of samples before fast Fourier transform (FFT) in real time spectral analysis to minimize spectral leakage and picket fence effect. Among all popular window functions, Kaiser-Bessel window is an obvious choice for its better spectral characteristics. In this paper, CORDIC (CO-ordinate Rotation DIgital Computer) based VLSI architecture for implementing Kaiser-Bessel window has been proposed for real time applications. The parallel-pipelined technique has been adopted for the present design to ensure high throughput. Various architectural design and implementation issues have been discussed. The physical synthesis for ASIC implementation of proposed architecture using Synopsys design compiler(Design Vision) and commercially available 0. 18 μm CMOS yields the core area of 52 mm 2and worst case dynamic power of 890 mW at an operating frequency and voltage of 400 MHz and 1.8 V respectively.