Description Of Processor Research Articles

Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions

Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions

Minimum device usages of field programmable gate array (FPGA) verification of multilevel PWM inverter drive generation

Space Vector Pulse-Width Modulation (SVPWM) has now become an unavoidable PWM in the power electronics inverter development. If the SVPWM implementation can be made user-friendly, the operation can be easily soaked in by the future researchers and also the closed loop operation becomes sophisticated. This paper conveys a broad view about the state of art of different Field programmable gate array (FPGA) processors along with the inner views about the implementations of the 3-level SVPWM. The description of the different processors is discussed along with the implementation variance and also attempts to implement the SVPWM through Xilinx Spartan-III 3AN-XC3S400 using MATLAB-Xilinx System Generator (XSG) without deploying the direct Very High Speed Language (VHDL) code. It provides shortest translation designs into hardware implementations that are faithful, synthesizable and efficient, which permits the designer to minimise the time spent for the description and implementation of circuit. The synthesis result shows that the proposed implementation at 50 MHz frequency operation consumes a power of 13mW and occupies 1112 look up tables (LUTs) and 424 File File (FFs). Thereby, the Total Resource Utilization reduced drastically to 36%, which is far better than the other existing implementations. Also, the inference of less processing time can be seen from the synthesis.

Thermodynamic cost of edge detection in artificial neural network (ANN)-based processors

ABSTRACT Architecture-based heat dissipation analyses allow us to reveal fundamental sources of inefficiency in a given processor and thereby provide us with road-maps to design less dissipative computing schemes independent of technology-base used to implement them. In this work, we study architectural-level contributions to energy dissipation in an Artificial Neural Network (ANN)-based processor that is trained to perform edge-detection task. We compare the training and information processing cost of ANN to that of conventional architectures and algorithms using 64-pixel binary image. Our results reveal the inherent efficiency advantages of an ANN network trained for specific tasks over general-purpose processors based on von Neumann architecture. We also compare the proposed performance improvements to that of Cellular Array Processors (CAPs) and illustrate the reduction in dissipation for special purpose processors. Lastly, we calculate the change in dissipation as a result of input data structure and show the effect of randomness on energetic cost of information processing. The results we obtained provide a basis for comparison for task-based fundamental energy efficiency analyses for a range of processors and therefore contribute to the study of architecture-level descriptions of processors and thermodynamic cost calculations based on physics of computation.

Hardware description of a simplified 4-bit softcore processor with BCD capabilities

The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the reduction of the execution clock cycles per instruction. Additionally, the assembler software was enabled to support macro-instructions to make easy the comprehension of some composed functions. As result, a very compact softcore processor was obtained, by means of a Verilog description done in a single file. This implementation occupies only the 2% of the medium-size FPGA used for the application, reaching a maximum possible working clock frequency of 929 Mhz.

P4-to-blockchain: A secure blockchain-enabled packet parser for software defined networking

Security is one of the most challenging issues in software defined networking (SDN), and causes include the inability to detect the contents of the packets. In addition, file transferring to SDN is a potential attack vector that can be exploited at the network level. On the SDN data plane (i.e. the switch), packets are processed so that their behavior in the network can be determined. Packet parser (PP) acts as the main role of this operation on the switch. PP plays a very important role in identifying packets and supporting protocols and testing new ideas in SDN, which requires packet parsers on the data plane to provide the necessary flexibility and programmability. In recent times, cryptographic ledger technology (also referred to as Blockchain in the literature) has been applied to securely transfer transactions and files in the networks, mainly for crypto payments. In this paper, we propose a new packet parser architecture called Blockchain-enabled Packet Parser (BPP) based on the security characteristics of the blockchain and support for data processing functions with the description of Programming Protocol-Independent Packet Processors (P4) language that has the BPP-independent attribute of the protocol. In the proposed architecture, we provide a mathematical model based on a multivariate correlation approach for attack detection from the observed packet traffic. The implementation of BPP architecture is on Field Programmable Gate Array (FPGA), which is known for its higher processing speed, flexibility, and lower consumption resources. The result indicates that the proposed BPP is able to detect attacks and policy performed on the control plane in how to detect an attack from a packet structure efficiently. Furthermore, the impact of the bandwidth with and without the BPP in hardware environment is evaluated to demonstrate BPP's efficiency.

The Response to Arbitrarily Bandlimited Gaussian Noise of the Complex Stretch Processor Using a Conventional Range-Sidelobe-Reduction Window

This paper derives a mathematical description of the complex stretch processor’s response to bandlimited Gaussian noise having arbitrary center frequency and bandwidth. The description of the complex stretch processor’s random output comprises highly accurate closed-form approximations for the probability density function and the autocorrelation function. The solution supports the complex stretch processor’s usage of any conventional range-sidelobe-reduction window. The paper then identifies two practical applications of the derived description. Digital-simulation results for the two identified applications, assuming the complex stretch processor uses the rectangular, Hamming, Blackman, or Kaiser window, verify the derivation’s correctness through favorable comparison to the theoretically predicted behavior.

Process vs. Processor Accounts of Stage Models: A Cautionary Tale. Commentary: Seeing changes: How familiarity alters our perception of change.

Process vs. Processor Accounts of Stage Models: A Cautionary Tale. Commentary: Seeing changes: How familiarity alters our perception of change.

Encriptación óptica de información con recuperación libre de ruido

The information protection systems based on optical processors, employing a double random phase mask encryption technique, allow data securely handling, but the recovery is not noise-free. Although the system security is provided by the optical processor enabling the information encoding, we demonstrate in this contribution that noise-free recovery is indeed possible by including the quick response coding, without altering the data protection process. The information to be protected is first converted into a quick response code or QR code, and then this code is optically encrypted. The decrypted QR code exhibits the usual noise produced by the random phase masks along with the involved opto-digital processing. Finally, when scanning the decrypted QR code we recover the original information without noise. We include the theoretical description of the optical processor, as well as we show experimental results that corroborate the validity and applicability of the security system.© 2015. Acad. Colomb. Cienc. Ex. Fis. Nat. All rights reserved.

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

Abstract The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.

Python to accelerate embedded SoC design

We present SysPy (System Python) a tool which exploits the strengths of the popular Python scripting language to boost design productivity of embedded System on Chips for FPGAs. SysPy acts as a “glue” software between mature HDLs, ready-to-use VHDL components and programmable processor soft IP cores. SysPy can be used to: (i) automatically translate hardware components described in Python into synthesizable VHDL, (ii) capture top-level structural descriptions of processor-centric SoCs in Python, (iii) implement all the steps necessary to compile the user's C code for an instruction set processor core and generate processor specific Tcl scripts that import to the design project all the necessary HDL files of the processor's description and instantiate/connect the core to other blocks in a synthesizable top-level Python description. Moreover, we have developed a Hardware Abstraction Layer (HAL) in Python which allows user applications running in a host PC to utilize effortlessly the SoC's resources in the FPGA. SysPy's design capabilities, when complemented with the developed HAL software API, provide all the necessary tools for hw/sw partitioning and iterative design for efficient SoC's performance tuning. We demonstrate how SysPy's design flow and functionalities can be used by building a processor-centric embedded SoC for computational systems biology. The designed SoC, implemented using a Xilinx Virtex-5 FPGA, combines the flexibility of a programmable soft processor core (Leon3) with the high performance of an application specific core to simulate flexibly and efficiently the stochastic behavior of large size biomolecular reaction networks. Such networks are essential for studying the dynamics of complex biological systems consisting of multiple interacting pathways.

Hardware Description of Multi-Directional Fast Sobel Edge Detection Processor by VHDL for Implementing on FPGA

The VHDL is an appropriate Hardware Description Language (HDL) for providing hardware models of practical image processing algorithms. The aim of this paper is to present hardware architecture of Sobel edge detection algorithm for implementing on field programmable gate array (FPGA) chips. The proposed architecture calculates the edges of gray scale images in four directions; vertical, horizontal, right diagonal and left diagonal. Simulation results and synthesizing proposed Sobel edge detection processor on Xilinx Spartan3 XC3S200 FPGA chip demonstrate the efficiency of proposed architecture for edge detecting of gray scale 1024×1024 images for real-time image processing applications. General Terms FPGA, Application Specific Processors, Image Processing.

Automatic generation of compiler backends

Application-specific instruction set processors have proven successful in meeting the various design constraints of modern embedded systems and often provide the only viable trade-off between computing power and opposing metrics such as power consumption. A promising approach to facilitate the exploration of processor design alternatives are processor description languages, which capture the instruction set and hardware organization of a processor. With the use of those processor models, various design tasks, for example, the adaption of software development tools, the generation of hardware models, and various verification tasks, can be automatized. These languages thus allow effective shortening of development turnaround times. In this work, the novel xADL language is presented, which, in contrast to most contemporary processor description languages, focuses on a structural modeling of the processor's hardware organization. However, a behavioral model of the instruction set is automatically derived using instruction set extraction. This provides a tight coupling between the structural hardware view and the instruction set view of the processor and reduces the complexity of processor models in comparison with existing languages. The feasibility of our approach is demonstrated by a compiler backend generator based on tree pattern matching. An important property of our generator is its ability to automatically verify whether the resulting compiler is complete, that is, it can process all possible input programs. The generated compilers are competitive to handcrafted production compilers, showing speedups of up to 20% for certain benchmarks. On average, moderate slowdowns between 3% and 15% have been observed for several processor models while considerable reductions in code size have been measured. Copyright © 2012 John Wiley & Sons, Ltd.

Processor Stew (review of Processor Description Languages by P. Mishra and N. Dutt, Eds.; 2008) [Book reviews

This is a review of Processor Description Languages (edited by Prabhat Mishra and Nikil Dutt). This book is likely to become the main resource for anyone wanting to understand the ADL area in detail. The book's 14 chapters contain detailed descriptions of 11 industrial and academic ADLs used for ASIP creation. In addition, it summarizes the salient features of eight more approaches in a concluding chapter. It thus can serve as the standard comparative reference work for this approach to processor-centric design for several years to come.

Design and implementation of an open CNC core at the shop floor level

In this paper, a new CNC core design method, the function-separated design (FSD) method, is proposed to increase the modularity and reconfigurability of CNC systems, simplify the CNC development process, as well as gain a secondary development ability to allow customers or third parties to add or modify NC functions at the shop floor level. With the FSD method, a new CNC core structure is built. In this structure, the CNC core is composed of three main components: engine machine interface, event processor (EP), and system description data (SDD). The engine machine interface provides an interface to machine tools through the parameter settings via a human machine interface (HMI). The EP and SDD are the most important parts. The SDD stores the control rules and modularized NC functions. It is designed as the relatively separated part inside the CNC core. It can also be modified according to the specification changes to access the functions of the CNC core at the shop floor level. To ease the modification of the SDD on the shop floor, the Statechart modeling tool is used to generate a CNC function model; meanwhile, an SDD generator is developed to convert this model into the SDD. The EP is driven by events from the event generator and processes these events by referring to the SDD. The EP always remains the same. With such a structure, the control rules and NC functions of a CNC core can be redesigned or upgraded easily. A case study for implementing a non-circular piston-turning system verifies the feasibility of the proposed design method at the shop floor level.

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

Today's Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which software tools, such as C compiler, assembler, linker, and instruction-set simulator, can be automatically generated. Among these tools, the C compiler is becoming more and more important. However, the generation of C compilers requires high-level architecture information rather than low-level details needed by simulator generation. This makes it particularly difficult to include different aspects of the target architectureinto one single model, and meanwhile keeping consistency. This paper presents a modeling style, which is able to capture high- and low-level architectural information at the same time and make it possible to drive both the C compiler and the simulator generation without sacrificing the modeling flexibility. The proposed approach has been successfully applied to model a number of contemporary, real-world processor architectures.

UML IN DESIGN OF ASIP

There are many possibilities how to describe the architecture of the embedded system eventually of the whole microprocessor. The description is realized usually using any special language, which only rarely provides a formal description of the architecture. The formal description is useful for an easily verification of the most critical parts of the architecture. Our task deals with the formal description of the Application Specific Instruction set Processors (ASIP) in UML. Due to the lower complexity of this type of processor, it is possible to generate automatically the software toolset from the model, which provide fluent development of the microprocessor's applications. The task is to provide the methodology for fully automatized design of microprocessor base on the UML description.

PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems

We have developed PGPG (Pipeline Generator for Programmable GRAPE), software that generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs). An FBCE typically consists of one or multiple FPGA (Field-Programmable Gate Array) chips and local memory. Here, the term “Field-Programmable” means that one can rewrite the logic implemented to the chip after the hardware is completed, and therefore a single FBCE can be used to calculate various functions, for example pipeline processors for gravity, SPH interaction, or image processing. The main problem with FBCEs is that the user needs to develop the detailed hardware design for the processor to be implemented to FPGA chips. The PGPG software generates all necessary design descriptions, except for the application software, itself, from a high-level design description of the pipeline processor in the PGPG language. The PGPG language is a simple language, specialized to the description of pipeline processors. Thus, the design of a pipeline processor in PGPG language is much easier than the traditional design. For real applications, such as the pipeline for gravitational interactions, the pipeline processor generated by PGPG has achieved a performance similar to that of hand-written code.

A formal concurrency model based architecture description language for synthesis of software development tools

Rapidly increasing design and manufacturing non-recurring engineering (NRE) costs are prompting a shift in electronic design from hardwired application specific integrated circuits (ASICs) to the use of software on programmable platforms. However, in order to minimize the power and performance overhead of such processors, we are seeing the introduction of domain or application specific processors such as network and communication processors. The design of such specialized processors requires software development tools such as simulators and compilers. In order to quickly develop these tools for multiple design points under consideration, it is highly desirable to have them synthesized from formal processor descriptions written in Architecture Description Languages (ADLs). In this paper, we present the Mescal Architecture Description Language (MADL). MADL features a two-layer structure, a core layer and an annotation layer. The core layer is based on a formal and flexible microprocessor model -- the operation state machine (OSM), which enables MADL to express the concurrency at the operation execution level for a wide range of architectures. We address the challenges faced in designing the core layer to combine the OSM model with techniques for achieving compact processor descriptions. The annotation layer features a generic syntax that allows creating annotation schemes to specify implementation dependent or tool specific information. To show the effectiveness of MADL, we present an MADL-based simulator synthesis framework that has been used to generate efficient cycle accurate simulators and instruction set simulators with very low development effort. We also describe our annotation schemes that enable the extraction of architecture properties for use in instruction scheduling and integer-linear-programming based register allocation. Our experimental results demonstrate the efficacy of MADL as a practical and promising language for the development of programmable platforms.

A Hybrid Energy-Estimation Technique for Extensible Processors

In this paper, we present an efficient and accurate methodology for estimating the energy consumption of application programs running on extensible processors. Extensible processors, which are getting increasingly popular in embedded system design, allow a designer to customize a base processor core through instruction set extensions. Existing processor energy macromodeling techniques are not applicable to extensible processors, since they assume that the instruction set architecture as well as the underlying structural description of the micro-architecture remain fixed. Our solution to the above problem is a hybrid energy macromodel suitably parameterized to estimate the energy consumption of an application running on the corresponding application-specific extended processor instance, which incorporates any custom instruction extension. Such a characterization is facilitated by careful selection of macromodel parameters/variables that can capture both the functional and structural aspects of the execution of a program on an extensible processor. Another feature of the proposed energy characterization flow is the use of regression analysis to build the macromodel. Regression analysis allows for in-situ characterization, thus allowing arbitrary test programs to be used during macromodel construction. We validated the proposed methodology by characterizing the energy consumption of a state-of-the-art extensible processor (Tensilica's Xtensa). We used the macromodel to analyze the energy consumption of several benchmark applications with custom instructions. The mean absolute error in the macromodel estimates is only 3.3%, when compared to the energy values obtained by a commercial tool operating on the synthesized register-transfer level (RTL) description of the custom processor. Our approach achieves an average speedup of three orders of magnitude over the commercial RTL energy estimator. Our experiments show that the proposed methodology also achieves good relative accuracy, which is essential in energy optimization studies. Hence, our technique is both efficient and accurate.

Techniques for accurate performance evaluation in architecture exploration

We present a system that automatically generates a cycle-accurate and bit-true instruction level simulator (ILS) and a hardware implementation model given a description of a target processor. An ILS can be used to obtain a cycle count for a given program running on the target architecture, while the cycle length, die size, and power consumption can be obtained from the hardware implementation model. These figures allow us to accurately and rapidly evaluate target architectures within an architecture exploration methodology for system-level synthesis. In an architecture exploration scheme, both the ILS and the hardware model must be generated automatically, else a substantial programming and hardware design effort has to be expended in each design iteration. Our system uses the Instruction Set Description language to support the automatic generation of the ILS and the hardware synthesis model, as well as other related tools.