PGPG: An Automatic Generator of Pipeline Design for Programmable GRAPE Systems

Abstract

We have developed PGPG (Pipeline Generator for Programmable GRAPE), software that generates the low-level design of the pipeline processor and communication software for FPGA-based computing engines (FBCEs). An FBCE typically consists of one or multiple FPGA (Field-Programmable Gate Array) chips and local memory. Here, the term “Field-Programmable” means that one can rewrite the logic implemented to the chip after the hardware is completed, and therefore a single FBCE can be used to calculate various functions, for example pipeline processors for gravity, SPH interaction, or image processing. The main problem with FBCEs is that the user needs to develop the detailed hardware design for the processor to be implemented to FPGA chips. The PGPG software generates all necessary design descriptions, except for the application software, itself, from a high-level design description of the pipeline processor in the PGPG language. The PGPG language is a simple language, specialized to the description of pipeline processors. Thus, the design of a pipeline processor in PGPG language is much easier than the traditional design. For real applications, such as the pipeline for gravitational interactions, the pipeline processor generated by PGPG has achieved a performance similar to that of hand-written code.