Deposition Of Passivation Layer Research Articles

UV-OZONE Treatment for Suppressing Surface Damages on Silicon Solar Cells.

In the preparation process of c-Si solar cells, qualified Si wafers must be processed through mechanical processing during manufacturing. Most of these processes involve mechanical processing, which inevitably results in severe mechanical damage layers and a wafer surface with large roughness. The current industry practice involves etching of the damage layer using an acid/alkali solution, and it is usually followed by deposition of additional passivation layers in the subsequent processes. However, even with these treatments, there still remain non-negligible microscopic saw damage and scratches on the wafer surface, which hinder the urgent development of a higher conversion efficiency of solar cells. Here, we provide a simple method to effectively suppress the impact of this surface damage. UV-OZONE treatment, which involves generation of an oxide layer and subsequent cleaning with hydrofluoric acid, leads to the effective regain of solar cell performance due to the passivation of dangling bonds and removal of sharp microstructures based on the creation of mechanical scratches. In addition, PEDOT:PSS/n-Si solar cells were prepared to exploit their strong surface dependence to investigate the effect of scratches on the overall performance. These results further validate the impact of scratches on solar cells, and a simple and effective method for surface damage suppression is provided.

Study on the performance of InGaN-based micro-LED by plasma etching combined with ion implantation process

This study utilized blue-light epitaxial wafers and employed semiconductor processes such as maskless laser writing, dry etching, wet etching, passivation layer deposition, electron beam evaporation, and ion implantation to fabricate micro-light emitting diode (μLED) arrays with different pixel sizes but the same emitting area (900 μm²). The μLED arrays with single pixel sizes of 5 μm, 10 μm, and 15 μm were fabricated, with array numbers of 6×6, 3×3, and 2×2, respectively. This study proposes etching the material in the channel region while retaining a certain width for implantation, known as the sidewall ion implantation process, aiming to achieve better insulation characteristics by using ion implantation technology to insulate the sidewall regions. It involves ion bombardment of the defect areas generated after plasma etching and the use of a passivation layer for protection. The isolation characteristics of μLED arrays processed by sidewall implantation exhibited better electrical isolation than those of μLED arrays processed only by plasma. The light output power, external quantum efficiency, and wall-plug efficiency were all superior for the sidewall implantation process when the device was miniaturized to 5 μm. Overall, the sidewall implantation process combined with plasma dry etching effectively improved the light output characteristics, with the enhancement ratio increasing as the device was miniaturized.

Boosting the responsivity of amorphous-Ga2O3 solar-blind photodetector via organosilicon surface passivation

In this paper, an amorphous Ga2O3 metal–semiconductor–metal photodetectors passivated by the organosilicon layer were reported. Due to the excellent passivation property of the passivation layer and the diffusion effect of hydrogen, the responsivity of Ga2O3 photodetectors was improved effectively, while the dark state current is basically unchanged. The results of x-ray photoelectron spectroscopy have proved that the amount of oxygen vacancy near the interface between organosilicon and Ga2O3 layer has been passivated and the surface chemisorption was suppressed via capping a foreign layer after the deposition of organosilicon passivation layer. The Ga2O3 photodetectors with organosilicon passivation layer exhibit a boosted performance, with a low dark current of 2.96 × 10−12 A, a responsivity of 11.82 A/W, and a specific detectivity of 9.01 × 1014 Jones.

(Invited) Micro-Transfer-Printing: A Novel Technology for Volume D2W Integration

In the past decade, the semiconductor industry has witnessed an ever-increasing demand in wafer-level integration and packaging technologies driven by increased requirements on functionality, performance, and efficiency. As one of the world’s leading specialty foundry groups for analog/mixed semiconductor technologies and more than thirty years of experience in volume manufacturing for automotive, industrial and medical applications, the X-FAB group has recognized this trend and broadened its offer accordingly. New integration techniques like wafer bonding, through-passivation vias (TSVs) processing, redistribution layers (RDLs) as well as the readiness to introduce new material systems like glass, polymers, noble metals, or compound semiconductors in a CMOS manufacturing environment clearly highlight the ongoing transformation process.Next to the stated, also Die To Wafer (D2W) integration technologies receive an increased interest and represent one additional topic of these developments. Especially the Micro-Transfer-Printing technology (also referred as mass transfer or just transfer-printing) gained particular interest and has seen comprehensive developments over the past years.To enable a heterogeneous chip integration, the micro-transfer-printing technology utilizes elastomeric stamps (see Figure 1 a; gray) with tunable adhesive properties to transfers devices or arrays of devices (commonly referred to as chiplets) from their native substrate (source wafer, orange) to a non-native target material (blue). This integration approach does not only enable heterogeneous 3D-wafer-level integration, it also provides several benefits like: high potential throughput since thousands of chiplets can be transferred in a parallel manner by the elastomeric stamp,the possibility to integrate smallest-scale devices,the opportunity to effectively utilize expensive source wafers and to transfer chiplets to multiple devices or target wafers,the high placement accuracy of 3σ < 1.5 µm, andthe opportunity to package devices with extremely short metallization tracks. To offer this versatile technology, X-FAB has set-up a µTP pilot line for the development and industrialization of related processes in the MEMS clean room facilities in Erfurt, Germany.Enabling an integration as depicted in Figure 1a) requires the development of several dedicated process sequences that have to be applied to source (orange) and target wafer (blue) to: form chiplets that are appropriate for integration via µTP, i.e. the source wafer has to be made “print-ready”,enable a high adhesion and thereby high print yield by adding a dedicated adhesion layer on the target wafer, andallow wiring and passivation of the integrated devices by subsequent adhesion patterning, redistribution layer (RDL) formation and passivation layer deposition. Out of the variety of potential integration option and material systems, X-FAB decided to focus on basically two integration scenarios, namely i) the preparation of print-ready SOI-based CMOS ASICs and ii) heterogeneous integration on CMOS wafers which both shall be explained in more detail within this presentation.The general process to make devices print-ready involves the chiplet singulation by multiple dry etches to form trenches down to handle wafer bulk material,the tether formation by SixNy deposition and patterning to form a mechanical system that holds the chiplet in place andthe wet chemical release etch to separate the singulated µIC from the handle wafer. Thereby, a print-ready µASIC is formed. It refers to a state in which the IC is separated from its original handle wafer and just kept in place by the tether systems as shown in Figure 1b. A basic requirement for the development of this process is the use of an SOI technology (such as X-FAB’s XT018), since the buried oxide layer (BOX) acts as the chiplet bottom protection in the final release etch.Next to the scope of providing X-FAB’s µASICs for an integration via transfer-printing, X-FAB is actively working on the assembly of III/V semiconductor elements/chiplets on CMOS ICs/ wafers to improve the performance of the available CMOS devices or even add new functionality. Based on the availability of print-ready III/V semiconductor chiplets provided by X-FAB’s foundry partners, the integration process involves the deposition of an adhesive layer on top of the CMOS wafer surface,the transfer-printing integration of the III/V chiplets,the final curing of the adhesive layer to adjust the material properties,the patterning of the adhesive by a dry etching process to open the CMOS wafer contact pads,the subsequent formation of a copper redistribution layer (RDL) andfinally, the passivation of the formed wafer-level package to protect the integrated chiplet and the metallization layer from environmental influences. An example of such an integrated wafer-level package (without passivation) is illustrated in Figure 1 c). Figure 1

A Cyclic Etching Process Using HFE-347mcc3 as a Lower-GWP Alternative to Perfluorocarbons for High-Aspect-Ratio SiO2 Features

As circuits continue to integrate at higher levels, the critical dimensions of DRAM and 3D-NAND are decreasing, leading to an increase in aspect ratios of various features such as contact holes and via holes in DRAM, and channel holes of stack layers in 3D-NAND. This trend has made the process of etching high-aspect-ratio SiO2 features more challenging. To achieve this, it is necessary to satisfy specific conditions including high selectivity to the mask or the underlayer film and the anisotropic etch profiles.Perfluorocarbons (PFCs) such as CF4 and c-C4F8 are commonly used for SiO2 etching. PFCs form a thicker steady-state fluorocarbon film on Si than SiO2, leading to high SiO2/Si selectivity. In addition, PFCs enable anisotropic etching since a passivation layer is formed on the sidewall, preventing lateral etching of the sidewall by chemical etchants.However, PFCs are a representative greenhouse gas with a high global warming potential (GWP) compared to CO2, causing significant adverse effects on global warming. Therefore, there have been efforts to reduce greenhouse gas emissions, such as setting goals for greenhouse gas reduction by each country through the Paris Agreement in 2015. Semiconductor manufacturers have also committed to reducing greenhouse gas emissions per silicon substrate area by 30% compared to 2010. In this regard, various studies are being conducted to develop a SiO2 etching process using alternative materials with lower GWP than PFCs. Fluorinated ethers and fluorinated alcohols are potential substitutes due to their low GWPs and short lifetimes. For example, heptafluoropropyl methyl ether (HFE-347mcc3) has a GWP of ~530 and an atmospheric lifetime of 5.2 years, significantly lower than those of PFCs.During etching of SiO2, the mask is susceptible to damage and corrosion by ions, resulting in various pattern deformations such as bowing, necking, and striation. These deformations adversely affect the miniaturization of the DRAM structure by reducing the process margin between holes and have a negative influence on the electrical characteristics of the device, such as contact resistance, line edge roughness, and line width roughness.To prevent these pattern deformations, the cyclic etching process that repeats the passivation layer deposition step and SiO2 pattern etching step was devised. A fluorocarbon film is deposited on the mask to protect it, then SiO2 is etched. The fluorocarbon film is deposited again to reinforce the mask and damaged fluorocarbon film during the etching process, and then SiO2 etching step is repeated to achieve the high-aspect-ratio SiO2 features.In this study, the cyclic etching process was conducted using HFE-347mcc3 as a lower-GWP alternative to PFCs to etch SiO2 contact holes. The effect of the duration of each step on the etch profile was investigated by adjusting the duration of the deposition and etching steps. This work demonstrated the feasibility of using HFE-347mcc3 as a lower-GWP alternative to PFCs for cyclic etching of SiO2 contact holes to obtain anisotropic etch profiles.

Effect of surface potential pinning on strain behavior of AlGaN/GaN device structures

Understanding the varied strain effects in AlGaN/GaN devices is crucial for realizing optimized flexible electronics systems and strain sensors. Here, we report on the effects of surface potential pinning, altered by the deposition of device-relevant SiNx passivation and Ni gate layers, on the strain-dependent carrier density, ns, of AlGaN/GaN two-dimensional electron gas structures. Flexible van der Pauw samples were made by separating AlGaN/GaN layers from the sapphire growth substrate using a two-dimensional boron nitride van der Waals release layer and transferring them to flexible substrates. For bare surface samples, we observed relatively large decreases in ns with tensile strain (Δns of −2 × 1011 cm−2 at 0.1% uniaxial strain), indicating an unpinned AlGaN surface potential. For the SiNx and Ni covered samples, the ns-strain trends were nearly flat, indicating a more pinned surface potential. Additionally, sub-bandgap 400 nm light is shown to effectively pin the surface potential as evidenced by flattening the ns-strain trend, the mechanism of which we explain in terms of the persistent photoconductivity effect. These observations could have important implications in tuning strain sensors and minimizing device variability in flexible electronics.

Emitter formation with boron diffusion from PECVD deposited boron-doped silicon oxide for high-efficiency TOPCon solar cells

We present a systematic study of emitter formation with dopant diffusion from boron (B)-doped hydrogenated silicon oxide (a-SiOx:H) deposited on textured n-type monocrystalline silicon (n-c-Si) wafers using a 13.56 MHz plasma-enhanced chemical vapor deposition (PECVD) system. The B atoms in the a-SiOx:H are activated and diffused into the n-c-Si wafer during a high-temperature annealing to form a p/n junction for solar cell application. Afterward, the B-doped SiOx layer is removed by hydrofluoric acid selective etching to obtain a clean surface for the deposition of AlOx passivation and SiNx antireflection layers. With the optimization of the PECVD deposition and the following annealing/etching processes, the B diffused region with a sheet resistance of 60–100 Ω/sq and a junction depth of 1.2–1.5 μm is obtained. A champion implied open-circuit voltage (iVoc) of 705 mV and a single-side saturated recombination current density (J0,s) of 17.6 fA/cm2 are obtained from a double-sided B diffused sample after the passivation with an atomic-layer-deposition (ALD) AlOx. In addition, the contact resistivity (ρc) at the metal/emitter interface is lower than 5 mΩcm2, where the metal contact is a Ti/Pd/Ag tri-layer structure. All of the material properties meet the requirements of high-efficiency solar cell. With the optimized emitter in the front, we made a SiOx and heavily phosphorus-doped polycrystalline silicon carbide (n-poly-SiCx) stack on the rear surface to form tunnel oxide passivated contact (TOPCon) solar cells. The results show that the iVoc of semi-finished TOPCon solar cell before metallization is more than 725 mV. Finally, a TOPCon solar cell with an efficiency of 24.24% is obtained, which is comparable with the TOPCon solar cells with the industrial thermally diffused emitter.

The effect of passivation-layer process to amorphous InGaZnO thin-film transistors using back-channel etch method

In this work, based on the channel damage caused by source/drain etching and passivation-layer deposition, the effects of the passivation-layer process on amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) devices were studied by combining experimental investigation with simulation verification. In terms of experimental exploration, it was found that the back-channel N2O plasma treatment had a significant impact on the performance of the device, which was difficult to control. Hence, to achieve a low cost, the entire back-channel process was directly carried out as two steps of SiO x passivation-layer deposition and final thermal annealing. In the aspect of simulation verification, the influence of the passivation-layer deposition radio-frequency (RF) power and the annealing effect on the internal mechanism of the device was studied based on a high-concentration doped defect density of states (DOS) model (doping level was N D = 1020 cm−3). The experimental results demonstrated that the high-performance of an a-IGZO TFT device can be achieved by adjusting the RF power of SiO x passivation-layer deposition. It was more important that annealing after passivation-layer deposition was a critical step in the manufacture of high-performance TFTs. The device exhibited the ideal performance after annealing under 1000 W RF power, with a threshold voltage of 5.65 V, a saturation mobility of 12.87 cm2 V−1s−1, a subthreshold swing of 0.88 V dec−1, and a current on-off ratio of 2.62 × 10°8. In addition, using the DOS model, it was found that the SiO x passivation-layer process had a significant impact on the DOS distribution and the carrier distribution in the channel, which in turn caused the threshold voltage to drift. At last, the high uniformity and stability of an a-IGZO TFTs array on glass were characterized.

Use of optical emission spectroscopy to predict silicon nitride layer properties

In this work, we use in-situ plasma characterization during SiNx passivation layer deposition in an industrial scale PECVD tool. Optical emission spectroscopy (OES) allows us to determine emission intensity of different species contained in plasma. We correlate these spectra peaks recorded by OES measurements with obtained layer properties: deposition rate, refractive index and bond densities. We select the appropriate OES features to be fitted to predict the layer characteristics using a large amount of OES data at different process conditions. We predict SiNx layer properties with maximum deviation of 10.3% for thickness, 1.7% for refractive index and 35.8% for bond densities. Based on these results, we propose OES as a powerful tool not only for process monitoring, but also for statistical modeling. Furthermore, using the same OES-based model, we realize process optimization for SiNx deposition by calculating a set of processing conditions giving layers with similar properties.

Impact of Passivation System on Device Performance and Proton Radiation Hardness in GaN-Based MIS-HEMTs

GaN-based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) are intensively investigated for high power, high frequency [1] and aerospace application [2] due to its wide bandgap, high breakdown field, and high carrier density and mobility at AlGaN/GaN interface [3]. For the demonstration of high power radio-frequency and aerospace applicable devices, the passivation layer introduced on the AlGaN barrier plays significant roles for the enhancement of the frequency characteristics [4] and proton radiation hardness [2]. From this point of view, diverse passivation materials and systems have been researched in GaN-based MIS-HEMTs [2, 5, 6]. However, the detailed impact of passivation layer on the device properties and the immunity to the proton irradiation is not clear in many cases, so far.In this work, we have prepared the SiN/Al2O3 bi-layer passivation system to study the impact of mechanical stress introduced by the passivation layer deposition on the device performance (Sample A: SiN = 20 nm, Sample B: SiN/Al2O3 = 5/15 nm, Sample C: SiN/Al2O3 = 5/35 nm). The correlation between the induced mechanical stress on the GaN channel and carrier transport properties in terms of carrier concentration and mobility at hetero-interface in GaN-based MIS-HEMTs was examined. The Al2O3 layer deposited by the atomic layer deposition (ALD) provided the tensile stress which compensated the compressive stress generated by the SiN layer deposited by the plasma enhanced chemical vapor deposition (PEDVD). When the compressive stress reduces through the deposition of Al2O3 on the SiN layer, the carrier concentration and mobility at hetero-interface were increased. With decreasing compressive stress, the piezoelectric field enlarges that enhances polarization charges [7] and carrier concentration. The carrier mobility was also improved with diminishing compressive stress since the mean free path related to the lattice scattering is decreased, enhancing transconductance as well. As a result, GaN-based MIS-HEMTs with slight tensile stress in Sample C exhibits the best device performance.The proton radiation hardness according to the passivation system was studied for various passivation systems. When we compared the device characteristics before and after the proton irradiation with the fluences of 1013 and 1014 cm-2 at an energy of 5 MeV, the device properties such as threshold voltage, drain current, and transconductance were changed. After the proton radiation, the threshold voltage was negatively shifted that is identical characteristics to the metal-oxide-semiconductor device [8], rather than GaN-based HEMTs [9] as relatively large amount of holes was trapped inside of the passivation system due to the lower hole mobility than electron. The alternation of the device characteristics depended on the passivation system. The ALD-deposited Al2O3 showed superior quality compared to the PECVD-deposited SiN that was revealed by the pulse-mode stress measurements. Therefore, the hole trap sites generated by the proton irradiation and located interior of the passivation system are less when the Al2O3 layer was employed as a passivation layer, showing smaller threshold voltage shift. Moreover, the carrier mobility deterioration caused by the Coulomb scattering between the trapped holes inside the passivation system and carriers at hetero-interface was improved with the Al2O3 passivation layer. The drain current and transconductance degradation were improved by applying Al2O3 passivation layer.Our systematic measurement results highlight that the optimized SiN/Al2O3 bi-layer passivation system is promising technique for the enhancement of the device performance and improvement of proton radiation hardness in GaN-based MIS-HEMTs.AcknowledgementThis work was supported by the National Research Council of Science & Technology (NST) grant by the Korean government (MSIP) (No. CRC-19-02-ETRI).

Improved Al2O3/SiNx and SiO2/SiNx stack passivation layer structure PERC sc‐silicon solar cells on mass production line

SummaryIn this study, we have successfully developed an industrially feasible stack rear Al2O3/SiNx and front SiO2/SiNx passivation layer PERC solar cells fabrication method based on the existing PERC sc‐silicon solar cells production line. The manufacturing parameters of the deposition processes were adapted to get the best passivation effect. The front SiO2/SiNx passivation layer deposition parameters were researched for the best front passivation effect. The fabrication parameters of the first high refractive index SiNx layer were improved. And a new thin low refractive index SiNx capping layer at SiO2/SiNx interface was introduced. Meanwhile, the stack rear Al2O3/SiNx layer structure with double SiNx layers was also researched, which exhibited good passivation results for the rich hydrogen content in high refractive index SiNx layer. The industrial stack passivation layers PERCs with new thin low refractive index SiNx capping layer possess good performances with an efficiency of 22.15%.

(Invited) Highly Stable Self-Aligned Top-Gate Indium Gallium Zinc Oxide Thin-Film Transistors for High-Resolution OLED TV and Mobile Displays

Highly stable self-aligned coplanar top-gate InGaZnO (IGZO) thin-film transistors (TFTs) with excellent threshold voltage (Vth) uniformity are developed by optimizing gate insulator film properties and controlling oxygen/hydrogen diffusion into IGZO channel. The TFTs do not show notable negative Vth shift and Vth non-uniformity from channel length 10 µm down to 3 µm. The TFTs also show no notable Vth shift during a humidity test in a chamber at 85°C/85% after deposition of passivation layers or even after 1-µm-thick thin-film encapsulation (TFE) SiNx layer on the top of the passivation layer due to the high quality/low hydrogen 2nd SiNx passivation layer deposited on the top of 1st SiOx passivation layer.

Impact of Passivation System on Device Performance and Proton Radiation Hardness in GaN-Based MIS-HEMTs

The impact of the passivation system on the device performance has been studied in GaN-based MIS-HEMTs using SiN/Al2O3 bi-layered passivation. The deposition of SiN and Al2O3 passivation layer induced the compressive and tensile stress on GaN channel layer, respectively. Through the Al2O3 deposition on top of SiN layer, the mechanical stress and device characteristics were modulated. The device properties such as carrier mobility and concentration at the hetero-interface were ameliorated when the slight tensile stress was applied on the GaN channel compared to the compressive stress. The proton radiation hardness corresponding to the passivation system was also researched. The SiN/Al2O3 passivation system exhibited stronger immunity to the proton radiation than that of SiN passivation due to the superior dielectric quality of Al2O3. These results highlight that the SiN/Al2O3 bi-layered passivation is promising technique for the optimization of the device performance and improvement of proton radiation hardness in GaN-based MIS-HEMTs.

Effect of Al2O3 deposition on carrier mobility and ambient stability of few-layer MoS2 field effect transistors

The effect of Al2O3 deposition on electrical properties and ambient stability of few-layer MoS2 transistors is investigated. The deposition of Al2O3 passivation layer by atomic layer deposition method resulted in the suppression of the hysteresis in the transfer curve and the enhancement of carrier mobility due to high-κ dielectric screening effect. In addition, the negative shift of threshold voltage (enhanced n-doping) and the metal-insulator transition at the carrier density n~1013 cm−2 is reported. The Al2O3 passivation layer helps electrical properties of MoS2 transistor are preserved even after 11 months. Al2O3 encapsulation provides a facile method to suppress extrinsic effect on the mobility of few-layer MoS2 transistors and to ensure the ambient stability.

Electrical properties of the HfO2/Al2O3 dielectrics stacked using single- and dual-temperature atomic-layer deposition processes on In0.53Ga0.47As

For sequential stacking of an Al2O3 passivation layer and a main HfO2 gate dielectric layer on In0.53Ga0.47As, we used single- and dual-temperature atomic-layer deposition processes, and systematically compared their effects on the dielectric-related electrical properties. When the deposition of Al2O3 passivation layer (approximately 0.7−0.8 nm) took place at relatively low temperatures of 100 °C, an increase in the subsequent deposition temperature for HfO2 (from 100 to 300 °C) assisted in decreasing both capacitance-equivalent oxide thickness and the number of bulk-related traps. However, the valuable reduction in both near-interface defect density and leakage current through the low-temperature Al2O3 passivation approach was monotonically lessened with an increase in the process temperature for the subsequent HfO2 deposition, which suggests the need for a careful optimization of a thermal budget for the dual-temperature process.

41.1: Invited Paper: Efficient pre‐treatment for improving the via hole profile in 4‐mask process TFT architecture

Ways to solve the passivation layer undercut in via hole were described in detail. By tuning the pretreatment before the passivation layer deposition, the passivation layer undercut in via hole was solved efficiently without any other side effects. Different from changing dry etching process parameters, we increasing the adhesion of the interface between metal layer and passivation layer to overcome undercut issue.

Area-Selective Deposition by a Combination of Organic Film Passivation and Atomic Layer Deposition

To enable the downscaling of Integrated Circuit (IC) components accordingly to Moore’s law, novel nano-patterning techniques and materials are essential. Self-Aligned patterning schemes, such as Area Selective Deposition (ASD), are receiving increasing attention due to challenges created by the continuous shrinking of critical dimensions (e.g. self-aligned vias to lines in multi-level interconnect architectures). In ASD, a given film is deposited exclusively on the desired growth area with respect to the non-growth area. Typically, this can be achieved by exploiting material properties, such as surface chemical composition variations, in combination with surface-sensitive deposition techniques, such as Atomic Layer Deposition (ALD). In addition, the ALD self-limiting half-cycle surface reactions provide a layer-by-layer growth mechanism, which is strongly dependent upon the chemical reactivity to the underlying layer. Intrinsic growth nucleation variations on different surfaces can be exploited in an ASD scheme, but this effect is typically limited to very few ALD cycles. In this talk, Self-Assembled Monolayers (SAMs) are evaluated as a passivation coating to extend the ASD process window. Potential applications that will be discussed are Copper passivation in a self-aligned via patterning process flow and area-selective bottom-up VIA fill in an interconnect metallization scheme.

Area-Selective Deposition by a Combination of Organic Film Passivation and Atomic Layer Deposition

Area-Selective Deposition (ASD) has the potential to enable self-aligned patterning schemes, which are implemented in the effort of keeping pace with the more and more challenging downscaling of the integrated circuit components. ASD can be achieved by exploiting surface-sensitive deposition techniques, such as Atomic Layer Deposition (ALD). However, the inherent selectivity of ALD is confined to very few ALD cycles (very thin films). Self-Assembled Monolayers (SAMs) are evaluated as a metal passivation coating to extend the ASD inhibition window. We present a successful strategy to achieve the selective deposition of Al oxide on Cu/SiO2 patterned substrate down to 50 nm half-pitch (HP) lines. We exploit the selective chemisorption of 1-octadecylthiol (ODT) on Cu to confine Al2O3 deposition on Si oxide. A study of ODT deposition on Cu allows to determine the best deposition conditions, which enable the demonstration of ASD of 6 nm Al2O3 film at relevant nano-scale dimensions. Selectivity toward Cu is demonstrated through the absence of Al signal in energy dispersive X-ray spectroscopy.

Effect of deposition temperature of a-Si:H layer on the performance of silicon heterojunction solar cell

Substrate temperature during intrinsic hydrogenated amorphous silicon (i-a-Si:H) passivation layer deposition by plasma enhanced chemical vapor deposition (PECVD) is found to be crucial for reaching high conversion efficiency (Eff) in a silicon heterojunction (SHJ) solar cell. Measurements from Fourier transform infrared (FTIR) and minority carrier lifetimes show that the good passivation properties of a-Si:H film deposited at lower substrate temperatures are achieved. The correlations between the optical and electrical properties of thin films and the performance of SHJ cells have been analyzed. Finally, a SHJ solar cell with an area of 242.5 cm2 was prepared at 210 °C, yielding a maximum cell conversion efficiency up to 23.3% with VOC of 741 mV, JSC of 38.49 mA/cm2 and FF of 82.0%.

Surface Modification of Hematite Photoanodes for Improvement of Photoelectrochemical Performance

Solar water splitting is a promising method for producing renewable fuels. Thermodynamically, the overall water splitting reaction is an uphill reaction involving a multiple electron transfer process. The oxygen evolution reaction (OER) has been identified as the bottleneck process. Hematite (α-Fe2O3) is one of the best photoanode material candidates due to its band gap properties and stability in aqueous solution. However, the reported efficiencies of hematite are notoriously lower than the theoretically predicted value mainly due to poor charge transfer and separation ability, short hole diffusion length as well as slow water oxidation kinetics. In this Review Article, several emerging surface modification strategies to reduce the oxygen evolution overpotential and thus to enhance the water oxidation reaction kinetics will be presented. These strategies include co-catalysts loading, photoabsorption enhancing (surface plasmonic metal and rare earth metal decoration), surface passivation layer deposition, surface chemical etching and surface doping. These methods are found to reduce charge recombination happening at surface trapping states, promote charge separation and diffusion, and accelerate water oxidation kinetics. The detailed surface modification methods, surface layer materials, the photoelectrochemical (PEC) performances including photocurrent and onset potential shift as well as the related proposed mechanisms will be reviewed.