Layer Deposition Of Oxide Research Articles

Characteristics and Formation of Thermal Oxidative Film Silicon Carbide for MOS Devices

In order to obtain the oxidation layer for SiC MOS, the oxide layers by thermal oxidation process with dry and wet method were deposited and characterized. Deposition temperature for oxidation layer was ~130 by and Ar atmosphere. The oxide thickness, surface morphology, and interface characteristic of deposited oxide layers were measurement by ellipsometer, SEM, TEM, AFM, and SIMS. Thickness of oxidation layer was confirmed 50nm and 90nm to with deposition temperature at and for dry 4 hours and wet 1 hour, respectively. For the high purity oxidation layer, the necessity of sacrificial oxidation which is etched for the removal of the defeats on the wafer after quickly thermal oxidation was confirmed.

Elementary reaction schemes for physical and chemical vapor deposition of transition metal oxides on silicon for high-k gate dielectric applications

This article describes the kinetics of reactions that result in substrate consumption during formation of ultrathin transition metal oxides on silicon. Yttrium silicate films (∼40 Å) with an equivalent silicon dioxide thickness of ∼11 Å are demonstrated by physical vapor deposition (PVD) routes. Interface reactions that occur during deposition and during postdeposition treatment are observed and compared for PVD and chemical vapor deposition (CVD) yttrium oxides and CVD aluminum-oxide systems. Silicon diffusion, metal-silicon bond formation, and reactions involving hydroxides are proposed as critical processes in interface layer formation. For PVD of yttrium silicate, oxidation is thermally activated with an effective barrier of 0.3 eV, consistent with the oxidation of silicide being the rate-limited step. For CVD aluminum oxide, interface oxidation is consistent with a process limited by silicon diffusion into the deposited oxide layer.

Self-ordered microcavities embedded in ultrashallow silicon p-n junctions

Scanning tunneling spectroscopy was used to obtain topographic images of the (100) surface of ultrashallow diffusion profiles of boron in silicon. This method makes it possible to study the influence of fluctuations of the surface deformation potential, which depend on the thickness of the preliminary deposited oxide layer and on the crystallographic orientation of the fluxes of nonequilibrium vacancies and self-interstitials that stimulate the exchange mechanisms of impurity diffusion. The existence of self-assembled systems of quantum anti-dots, which are formed due to fluctuations in the surface deformation potential and which are microdefects that penetrate through the diffusion profile of the dopant, is demonstrated for the first time. It is established that a spread in the sizes of quantum anti-dots is reduced with increasing temperature of the impurity diffusion. In addition, the sizes of quantum anti-dots are found to be interrelated to their spatial distribution, which is indicative of a fractal mechanism of formation of self-assembled zero-dimensional systems under conditions of strong interaction of the flux of impurity atoms with that of primary defects. Self-assembled quantum anti-dots embedded into a system of silicon quantum wells make it possible to design microcavities with distributed negative feedback; the existence of such microcavities is confirmed by spectral dependences of the reflection and transmission coefficients in the visible and infrared regions of the spectrum, respectively.

4H-SiC n+pp+ structure passivated with a SIPOS-SIO2 compound layer

In this article, a semi-insulating polycrystalline silicon (SIPOS)-SiO2 compound sheet is used for the first time as a passivating layer of a 4H-SiC n+pp+ structure. After the deposition of SIPOS by LPCVD, a unique thermal oxidation step, annealing in oxygen atmosphere at 900 °C instead of the normal method of oxide layer deposition, is adopted to grow an SiO2 layer over it. The passivation result demonstrates the reasonableness of the alternation. Moreover, chief technological parameters that influence the passivating effect are adjusted and conclusions are drawn that there should be excess oxygen in the SIPOS layer and its deposition temperature should be lower than 1000 °C. The annealing temperature should be high, up to 900 °C. Experimental data show that a SIPOS-SiO2 compound layer can act as an effective passivation sheet of the 4H-SiC n+pp+ structure to obtain an ideal breakdown voltage and leakage current.

High-resolution transmission electron microscopy/analytical electron microscopy characterization of epitaxial oxide multilayers fabricated by laser ablation on biaxially textured Ni

Microstructural characterization of rolling-assisted biaxially textured substrates (RABiTS) was conducted using high-resolution transmission electron microscopy (TEM) and high-resolution analytical electron microscopy (AEM). RABiT substrates with a multilayer configuration YSZ (0.2 μm)/CeO 2 (0.9 μm)/Ni (125 μm) were studied. The substrates were fabricated by epitaxial deposition of oxide layers using laser ablation on biaxially textured Ni substrates. High critical current density YBa 2Cu 3O x thick films have been fabricated on such RABiT substrates and typically yield J c values over 1 MA/cm 2. TEM examinations show that a reaction layer 10–40 nm thick is formed at the CeO 2/Ni interface. Detailed microstructural and chemical analyses indicate that the layer is epitaxial {001} nickel oxide on {001} Ni. The CeO 2 layer is found to consist of three distinct morphologies corresponding to the growth atmosphere during the deposition. The YSZ layer exhibited a columnar structure aligned along the [100] axis, with little or no orientation variation between the columns. The interface between the YSZ and CeO 2 layers is atomically sharp and neither interdiffusion of elements nor an interfacial reaction layer is observed. Implications of these results on processing are discussed.

High Voltage Silicon Carbide Devices

ABSTRACTProgress made in the development of high performance power rectifiers and switches from silicon carbide are reviewed with emphasis on approaching the 100-fold reduction in the specific on-resistance of the drift region when compared with silicon devices with the same breakdown voltage. The highlights are: (a) Recently completed measurements of impact ionization coefficients in SiC indicate an even higher Baliga's figure of merit than projected earlier. (b) The commonly reported negative temperature co-efficient for breakdown voltage in SiC devices has been shown to arise at defects, allaying concerns that this may be intrinsic to the material. (c) Based upon fundamental considerations, it has been found that Schottky rectifiers offer superior on-state voltage drop than P-i-N rectifiers for reverse blocking voltages below 3000 volts. (d) Nearly ideal breakdown voltage has been experimentally obtained for Schottky diodes using an argon implanted edge termination. (e) Planar ion-implanted junctions have been successfully fabricated using oxide as a mask with high breakdown voltage and low leakage currents by using a filed plate edge termination. (f) High inversion layer mobility has been experimentally demonstrated on both 6H and 4H-SiC by using a deposited oxide layer as gate dielectric. (g) A novel, high-voltage, normally-off, accumulation-channel, MOSFET has been proposed and demonstrated with 50x lower specific on-resistance than silicon devices in spite of using logic-level gate drive voltages. These results indicate that SiC based power devices could become commercially viable in the 21st century if cost barriers can be overcome.

Optimization of intermetal dielectric deposition module using simulation

A major challenge arising in the interlevel dielectric deposition processes in modern multilevel very large scale integrated technology is the filling of high aspect-ratio spaces without voids between metal lines. Here the main concerns are step coverage and material properties of dielectric films. One approach is the multistep silicon dioxide deposition using plasma enhanced chemical vapor deposition followed by atmospheric pressure CVD from ozone/TEOS. To combine the advantages of different processes and to satisfy the device reliability requirements, one needs to optimize the relative thickness of these sequentially deposited oxide layers. In this work a profile simulator, SPEEDIE, is employed to study this multistep process. For the PECVD process a free molecular-flow model based on the combination of a single sticking-coefficient LPCVD model and an ion-induced-deposition model is used. For the atmospheric pressure CVD (APCVD) process a continuum transport model considering both gas-phase diffusion and surface reaction is used with a geometry-variant reaction rate which depends on the ozone (O3) concentration. The major topography-controlling parameters are calibrated for these sequential processes, and verified through simulation. As an example of application, a prediction of void-forming based on the reliability requirements is generated by the simulator, and can be regarded as a measure of this multistep process. In general an efficient design tool is provided to help optimize the interlevel dielectric deposition processes.

Deposition of Oxide Layers by Computer Controlled"Injection-LPCVD"

A new process for stable generation of precursor's vapour pressure for CVD thin layers synthesis is experimented. The vapour pressure is controlled by sequential computer-driven injection of precise micro amounts of liquid in an evaporator, where flash volatilization occurs. During deposition, the precursors are maintained at room temperature under inert gases in an hermetically closed vessel: even thermally unstable precursors may be used. The results reported here are focused on the OMCVD deposition of Ta 2 O 5 . The growth rate increases up to 11 μm/h at 650°C (amorphous layers), and decreases above (crystallized layers). In a second part, we demonstrate the feasibility of Ta 2 O 5 /SiO 2 multilayers using two injectors.

Pulsed laser deposition of YBa/sub 2/Cu/sub 3/O/sub 7-δ//BaTiO/sub 3//YBa/sub 2/Cu/sub 3/O/sub 7-δ/ multilayer structure on Si(100) substrates

We have studied materials issues relevant to the applications of YBCO/BTO/YBCO multilayer structures, including multilayer HTS circuits and crossovers, nonvolatile memories, and on-chip energy storage for Si solar cells. Due to the good lattice match between BTO and YBCO, epitaxial YBCO/BTO multilayer device structures are possible. We have deposited YBCO/BTO/YBCO capacitors onto YSZ buffered Si substrates by using pulsed laser deposition technique. All four oxide layers are grown in situ without breaking the vacuum, and without lowering the substrate temperature to below 600/spl deg/C. We have achieved sharp resistive transitions for both the top and the bottom YBCO layers with onset at 90 K, zero resistance at 89 K for the bottom layer and 88 K for the top layer. X-ray diffraction data indicate that all four deposited oxide layers have their c-axis perpendicular to the substrate, and have less that 10% in-plane misorientation. The BTO layer shows a dielectric constant of 210, a leakage constant of 5/spl times/10/sup -7/ A/cm/sup 2/ at 10 Volts, and a remanent polarization of 26 /spl mu/C/cm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pulsed Laser Deposition of Ferroelectric Multilayer Capacitors YBa2Cu3O7−δ/BaTiO3/YBa2Cu3O7−δ on Si(100) Substrates

ABSTRACTFerroelectric multilayer capacitors (YBCO/BTO/YBCO) are fabricated on YSZ buffered Si (100) substrates by using pulsed-laser deposition technique. The deposition process is monitored in situ by using a Fourier Transform Infrared Spectrometer (FTIR), which measures the film's deposition rate and dielectric constant during the growth process. All four oxide layers in such a multilayer capacitor are grown in situ without breaking the vacuum, and without lowering the substrate temperature to below 600°C. The electrical properties and microstructures of the multilayer capacitor are studied and the optimal deposition condition are identified. Sharp resistive transitions are achieved for both the top and the bottom YBCO layers with on-sets at 90 K, zero resistance at 89 K for the bottom layer and 88K for the top layer. X-ray diffraction θ-2θand φ scans indicate that all four deposited oxide layers have their c-axis perpendicular to the substrate, and have less that 10% in-plane misorientation. The dielectric constant of the BTO layer is over 210. Hysteresis P-E characteristics and current-voltage curves are also measured to determine dielectric properties of the barium titanate films. Preliminary results with LaSrCoO (LSCO) electrode layer are also presented.

Thermal Annealing Effects on the Mechanical Properties of Plasma‐Enhanced Chemical Vapor Deposited Silicon Oxide Films

An annealing study was performed on nonstoichiometric amorphous films fabricated by plasmaenhanced chemical vapor deposition (PECVD) at 300°C using and chemistry. After deposition, these layers contain hydrogen and nitrogen impurities, which were found to play a major role in the explanation of the properties of annealed films. Fourier transform infrared absorption spectra of plasma enhanced vapor deposited oxide layers annealed at elevated temperatures show approximately the same features as the spectra of thermal oxide films. This similarity demonstrates the ability of PECVD oxides to form a regular network of Si‐O tetrahedrals. From distinct deviations in these spectra, the participation of Si‒N bonds located within the Si‒O network is concluded. The participation of Si‒N bonds is also confirmed by the estimation of the activation energies in wet chemical etching studies using ammonium hydroxide water solution. The mechanical stress of the PECVD oxides clearly depends on the deposition conditions and their thermal history. With increasing annealing temperature the intrinsic stress increases until a maximum film stress value is reached between 700 and 800°C. Above this temperature the intrinsic stress is continuously reduced until the total stress approaches the value of the thermal film stress. This is explained mainly by hydrogen desorption, Si‒N bond formation, and bond rearrangement processes. Depending on deposition conditions and postannealing steps, it is possible to design layers with a predefined stress.

Suppression of Water Absorption in Borophosphosilicate Glass Thin Layers with High Boron Concentration

A method for encapsulating a borophosphosilicate glass (BPSG) layer on a silicon substrate is demonstrated. The deposition of BPSG film using low‐pressure chemical vapor deposition on silicon wafers is immediately followed by a thin, undoped silicon oxide layer deposition. The sequential deposition in the same reactor tube eliminates exposure of the BPSG film to the ambient air. The capping oxide suppresses water absorption in the underlying BPSG glass layer, thereby allowing more than 5 weight percent of boron to be incorporated into the BPSG film. The obtained layers are chemically stable and satisfy requirements for the low thermal budget interlevel dielectric.

The high temperature aqueous corrosion of ferritic steels: Effect of heat flux on corrosion and magnetite deposition

A length of 9Cr-1Mo ferritic steel tube has been exposed to a wide range of heat fluxes (0–1389 kW m −2) under realistic steam generator conditions (355°C, 17.6 MPa, subcooled boiling to 15% steam quality) for 3906 h. Deposition of magnetite on to the tube surface was found at first to increase rapidly with heat flux. At higher heat fluxes the rate of increase slowed down and a maximum was attained at ∼ 1200 kW m −2. The results can be understood in terms of concentration and dryout processes beneath growing steam bubbles. The rate of corrosion was found to be inversely proportional to the deposited oxide thickness and thus consistent with a reaction controlled by diffusion of water molecules through the deposited oxide layer. Particles of metallic iron, observed in the middle oxide layer at high heat fluxes, are thought to be a consequence of the limited diffusion routes for H 2O through the outer layer and the formation of hydrogen within the oxide.

The effects of subcutaneous oxidation at the interfaces between elemental and compound semiconductors and SiO2 thin films deposited by remote plasma enhanced chemical vapor deposition

We have observed that in the low-temperature deposition of thin films of SiO2 onto semiconductor surfaces by remote plasma enhanced chemical vapor deposition, oxidation occurs at the semiconductor–SiO2 interface. This subcutaneous process generates a thin film of native oxide, which can then play a significant role in determining the electrical properties of the semiconductor/oxide interface. The native oxide formed on Si is SiO2, and we have determined that the growth of this oxide does not interfere with the formation of device quality interfaces provided that the thickness of the deposited oxide layer is less than ∼250 Å. For an oxide thickness greater than ∼250–300 Å, trapping states associated with defects produced along with the subcutaneous oxidation degrade the properties of the Si/SiO2 interface. The native oxide that forms on Ge surfaces during SiO2 depositions is the water-soluble, rutile-structured form of GeO2, and the presence of this oxide significantly degrades the electrical quality of the Ge/dielectric interface. In the case of the compound semiconductor interfaces with deposited SiO2, native oxide formation also generally degrades the electrical characteristics. For example, the oxide that forms on GaAs is predominantly Ga2O3, whereas the oxide on CdTe displays both Cd–O and Te–O bonding. Interposing a thin layer of epitaxial, and pseudomorphic Si between a Ge, GaAs, or CdTe semiconductor surface and the deposited SiO2 film, can provide a viable approach to the formation of good metal–oxide-semiconductor (MOS) devices, provided that the subcutaneous oxidation of the Si layer that occurs during oxide deposition does not ‘‘punch through’’ that layer and thereby allow for the oxidation of the underlying Ge, GaAs, or CdTe substrate as well.

Spacing dependence of magnetic recording with a single thin-film head and disk (abstract)

Although it is known that magnetic recording system performance can be improved by reducing the separation between the head and media, few detailed measurements of the spacing dependence of recording performance (rolloff curves, isolated pulse heights and widths, etc.) have been made. Most measurements reported to date are at low linear velocities using flexible media and deposited oxide layers on the head1 or carbon overcoats of various thicknesses on the flexible disk2 to maintain a given spacing. This paper presents the results of measurements made with a novel device which positions the head at arbitrary (and continuously variable) heights above a rigid magnetic disk operating at a high and constant linear velocity. Separate read and write spacing loss measurements were made using a 3380-type thin-film head and metal film disk at a number of spacings ranging from 0.075 μm (3 μin.) to 0.5 μm (20 μin.). The results are analyzed using head sensitivity functions computed by the boundary element method. Good agreement between theory and data is found at linear densities in excess of 2500 fc/mm. The advantages of magnetic recording at small head/disk spacing are discussed.

Oxide/aqueous solution interfaces, interplay of surface chemistry and electrocatalysis

A number of insoluble, conducting transition metal oxides have acquired primary importance in electrochemical technology. So-called activated electrodes are prepared by depositing oxide layers on “inert” supports (Ti, Ta, Nb, etc.) by thermal decomposition of suitable precursors. The resulting oxides are non-stoichiometric, the temperature and procedure of preparation being crucial variables. Separation of true catalytic effects from the apparent ones due to geometric factors is needed for a proper understanding of the factors governing the catalytic activity. The acid-base properties of oxides in contact with aqueous solutions depend intimately on the surface structure. Being intensive properties they are not affected by geometric factors. Any variation of these properties with temperature and procedure of oxide preparation can thus be associated with modifications in the catalytic properties. This idea is illustrated by a number of examples for the oxides of highest technological interest: RuO 2 (primary active component of the so-called ‘Dimensionally Stable Anodes’), IrO 2, IrO 2 + RuO 2, Co 30 4, NiCo 2O 4.

Effects of Si Implantation on Sb Diffusion In Sb-Silica Spin-On Layers

AbstractThe effects of Si implantation (2×1015 · cm-2) on the diffusion of Sb in Sb doped silica (SiO2) spin-on layers and on their hardness were studied. RBS analysis and AES depth profiling showed that the implantation greatly retarded the Sb diffusion (1000–1200°C, 10 sec) in the oxide layer. Hence the high level of Sb near the SiO2/Si interface, which is clearly seen for the unimplanted part of the sample was not noticible in the non implanted part. AES depth profile measurements also showed that the deposited oxide layers were more sputter resistant as a result of the implantation. The above observations are related to the ion induced radiation damage.

The effect of chemical surface treatments on non-native (Bi2O3) GaAs metal-insulator-semiconductor solar cells

GaAs metal-insulator-semiconductor solar cells with a physically deposited Bi2O3 interfacial layer have been investigated. The deposition techniques used in the study were electron beam and boat thermal evaporation. The cells fabricated with interfacial layers of Bi2O3 showed a substantial improvement in open-circuit voltage over cells made without the physically deposited oxide layer. An etch has been used which yields an irregular ’’textured’’ surface. Cells employing this surface had a higher short-circuit current than those made with smooth, polished surfaces. The open-circuit voltages of these textured cells were lower than those with smooth surfaces. Calculations of the dependence of open-circuit voltage on pinhole density are in agreement with these results since a rough surface has a greater probability of pinholes.

X-ray Diffraction Topography of Germanium Wafers

X-ray diffraction topography in transmission and reflection has been employed to analyze crystal faults and stresses in germanium wafers caused by deposition of oxide layers, epitaxy and planar diffusion. Localized diffusion of arsenic, gallium and phosphorus normally does not introduce stresses sufficiently high to generate dislocations in germanium (011) wafers. However, heat treatment of germanium wafers covered with a SiO2 film causes high stresses which are often relieved by plastic deformation.