Deposited Silicon Nitride Layer Research Articles

Advanced optical modelling of dynamically deposited silicon nitride layers

Dynamic deposition of silicon nitrides using in-line plasma enhanced chemical vapor deposition systems results in non-uniform structure of the dielectric layer. Appropriate analysis of such layers requires the optical characterization to be performed as a function of the layer's depth. This work presents a method to characterize dynamically deposited silicon nitride layers. The method is based on the fitting of experimental spectroscopic ellipsometry data via grading of Tauc–Lorentz optical parameters through the depth of the layer. When compared with the standard Tauc–Lorentz fitting procedure, used in previous studies, the improved method is demonstrating better quality fits to the experimental data and revealing more accurate optical properties of the dielectric layers. The most significant advantage of the method is the ability to extract the depth profile of the optical properties along the direction of the layer normal. This is enabling a better understanding of layers deposited using dynamic plasma enhanced chemical vapor deposition systems frequently used in the photovoltaic industry.

Fabrication and characterization of PECVD silicon nitride for RF MEMS applications

The structural, optical and electrical properties of plasma enhanced chemical vapor deposited silicon nitride layers are investigated, which have been used as a dielectric layer during RF MEMS fabrication. During growth, the gas ratio (SiH4/NH3) is varied between 0.33 and 0.5 and pressure is varied between 400 and 700 mTorr while deposition time is kept constant. The results in the films show differing properties. The thicknesses of the resultant films are between 150 to 220 nm with different gas flow ratios and pressures whereas the deposition time was kept constant. A Bruggeman effective medium approximation is utilized to model the refractive index of the films. Reflectance measurements were carried out in the range of 210–250 nm. The refractive indexes of the films varied between 1.79 and 2.03, with a dielectric constant varying from 6.66 to 7.22. Capacitance voltage measurements yield a fixed dielectric charge value in the low −1012 cm−2 while a breakdown voltage of 915 V μm−1 is achieved for films grown at the lowest gas ratio and pressure. The quality of Si/SixNy interface is also considered.

Fabrication of a Nanosize Pattern Embedded Plastic Chip via an Injection Molding Method for Application to an Optical Biosensor

Abstract We demonstrate a commercialized injection molding method for nano patterning of polymethyl methacrylate (PMMA) for the purpose of mass production of a label-free optical biosensor chip. Scanning electron microscope (SEM) images clearly show uniform nanopattern transfer on the plastic chip fabricated by an injection molding method. A uniformly deposited silicon nitride layer having a high refractive index by a plasma enhanced chemical vapor deposition (PECVD) technique is also observed. A unique characterization method is described wherein optical resonance reflection is used accurately and quickly to characterize the geometrical sensor structure. The authors anticipate that this robust method will provide an excellent means of producing an optical resonance reflection biosensor (ORRB).

Wafer-level flame-spray-pyrolysis deposition of gas-sensitive layers on microsensors

This paper presents a CMOS-compatible wafer-level fabrication process for monolithic CMOS/MEMS sensor systems coated with sensitive layers directly deposited by means of flame spray pyrolysis (FSP). Microhotplate (µHP)-based devices, featuring an FSP directly deposited SnO2/Pt layer, have successfully been realized on a wafer level. The thermal characterization evidenced a thermal resistance of 10.6 °C mW−1; moreover, gas test measurements with ethanol have been performed. Microhotplate membrane deformations during device operation have been investigated and have been reduced by adjustment of the intrinsic stress of a deposited silicon nitride layer.

Generic technological platform for microfabricating silicon nitride micro- and nanopipette arrays

In this paper, the design and the characterization of batch fabricated SixNy micropipette arrays with diameters ranging from 6 µm down to 250 nm are described. The process used to fabricate the micromachined pipettes includes a deep reactive ion etching step, followed by the deposition of two successive layers, a thermal oxide layer and a low stress, low pressure chemical vapor deposited silicon nitride layer, respectively. The diameter of the micropipettes could be modulated simply by choosing the thicknesses of the oxide sacrificial layer and of the nitride walls of the micropipettes. The reactive ion etching of the micropipette top layer in deep cavities and in confined and deconfined configurations is discussed. The mechanical resistance of the micropipette array was qualitatively tested and it was demonstrated that a force of 0.25 mN/micropipette could be applied without rupture of the micropipettes.

P‐111: A Thin Film Encapsulation Stack for PLED and OLED Displays

AbstractFor a thin film (< 1 μm) encapsulation stack consisting of only 3 plasma deposited silicon nitride layers separated by a thin (< 100 nm) organic layer, a water permeation rate of below 10−5 g/m2 per day at 50 °C and 50% rH has been measured using the Ca test. PLED lifetimes of over 500 hours at 60 °C and 90% rH have been reached locally. While the Ca test indicates that pinhole free encapsulation is possible, edge and particle related defects still forecast a challenge for device encapsulation.

Physical and electrical characterisation of oxynitride films produced by plasma oxidation of deposited silicon nitride layers

LPCVD silicon nitride films have been oxidised in an oxygen plasma using low thermal budget plasma anodisation to produce oxynitride films. The electrical integrity of these films was generally shown to improve following oxidation and a model of the conduction processes in the oxynitride has been suggested.

Highly uniform E/D MESFETs by Si ion-implantation and methane/hydrogen plasma gate recessing

A methane/hydrogen (CH4H2) plasma has been used for the gate recessing of E/D MESFETs fabricated on a highly uniform active layer formed on a semi-insulating LEC grown GaAs substrate by Si ion-implantation through an excellent plasma enhanced chemical vapour deposited silicon nitride layer and rapid thermal annealing with the same layer as cap. Threshold voltage standard deviation ( sigma Vth) as low as 16 and 31 mV, over a full 5 cm wafer, has been achieved for respectively E and D MESFETs with a gate length of 1.5 mu m.

Damage effects in silicon and MNOS structures caused by beams of ionized and neutral argon atoms with energies below 5 keV

Low energy ion and/or atom beams (2–5 keV) produced by saddle field ion sources have been used to study the damage effects of ion/atom beam milling on single crystal silicon wafers either uncoated or with both thermal oxide and deposited silicon nitride layers on the surface. MeV ion channelling techniques and transmission electron microscopy have been applied to assess the total disorder, argon retention and microstructure of the damage in the uncoated wafers before and after annealing. Capacitance voltage measurements (1.3 MHz and quasi-static) have been made on MNOS structures after ion and atom beam milling. Specimens bombarded with atoms show smaller flatbed shifts than those bombarded with ions of the same energy and dose. The results are interpreted in terms of field assisted injection of charge carriers during bombardment and preferential removal of positive space charge (holes) during low temperature annealing.

A metal-insulator-silicon junction seal

Most semiconductor devices today have a costly vacuum-tight encapsulation that provides a microenvironment for high reliability and electrical connections to the circuit in which it is used. A junction seal consisting of a metal-insulator-silicon (MIS) system of materials has been developed to replace the vacuum-tight encapsulation. The MIS junction seal, consisting of platinum silicide-titanium-platinum-gold contacts and a Silicon nitride overcoat, provides the necessary encapsulation for high reliability. Electrical and mechanical connections are provided by gold beam-deads. During fabrication, the contact windows are opened in the deposited silicon nitride layer either by etching with boiling phosphoric acid using SiO 2 as a mask or by anodically converting the silicon nitride in the windows to a soluble oxide. The multilayer contact is then applied to complete the junction seal. The initial characteristics of sealed-junction transistors fabricated by the above methods were similar to those of the unsealed transistors. The reliability of the sealed-junction transistors determined by accelerated aging after an intentional sodium contaminafion of 1017atoms/cm2surpassed that of the standard silicon planar transistors sealed in a vacuum-tight enclosure.