Depletion-mode Devices Research Articles

AlGaN High Electron Mobility Transistor for High Temperature Logic

We report on AlGaN HEMT-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data revealed the GaN-channel HEMT experienced a 6.9× reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200 nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

Photovoltaic Bias for Depletion-Mode Devices in Low-Noise Amplifier Applications [Application Notes

It can be a designer’s nightmare: choosing a high-performance microwave transistor to design a low-noise amplifier (LNA) or a transmitter output stage, only to find out that many of them are depletion-mode devices. These require an additional negative voltage since the gate bias must be of the reverse polarity to the drain one. When a single power supply is used for such a device, which is typically the only viable solution, generating additional negative voltage can be a challenging task because it quickly increases the complexity and cost. Furthermore, a switching power supply (the most common solution to this problem) demands sufficiently large capacitors for reliable operation and noise filtering. However, large capacitor values in bias networks might affect amplifier stability and so introduce an extra challenge that engineers quickly overlook.

(Digital Presentation) Liquid-Metal-Printed Ultra-Thin ITO-Thin-Film Transistor

Indium oxide is one of the promising materials for the n-channel layer for high-mobility oxide-TFT because of its high electron mobility characteristics due to the nature of spatially spread-In 5s orbital. However, excess carrier electrons in In-based channels cancel field-effect gate modulation and causes the formation of a short depletion layer. Moreover, it is challenging to reduce the electron density without the degradation of electron transport. Therefore, developing fully-depletion operated TFT using an ultra-thin channel is a straightforward strategy to demonstrate the high potential of In-based materials for TFT applications.In this work, we developed an ultra-thin tin-doped Indium oxide (ITO) channel (~ 1.9 nm-thick.) and demonstrated a fully-depleted ITO-TFT exhibiting high mobility of 27 cm2/Vs. The ITO channel was grown by a cost-effective vacuum-free liquid-metal-printing route at the maximum process temperature of ~ 200 oC in an ambient atmosphere. Post-thermal annealing in air made significant improvement of device characteristics originating from the reduction of shallow acceptor-like in-gap defects in the ITO channels, and high-performance n-channel ITO-TFT with a large on/off-current ratio of 109 and a sharp threshold slope was achieved. By controlling air-annealing temperature, we also successfully fabricated both enhancement and depletion-mode devices and developed a full signal swinged-oxide-NMOS inverter composed of a depletion-load structure.

Improved Breakdown Voltage and Low Damage E-Mode Operation of AlON/AlN/GaN HEMTs Using Plasma Oxidation Treatment

Low-damage plasma oxidation treatment for AlN/GaN high-electron-mobility transistors (HEMTs) was developed in this letter, with which high-performance enhancement-mode (E-mode) AlON/AlN/GaN HEMTs were demonstrated. After removal of in situ SiN cap layer within gate area, remote plasma oxidation (RPO) treatment of 4.9nm AlN barrier layer at 300 °C leads to formation of AlON insulator layer and effective depletion of 2-D electron gas channel, without etch-induced damage or serious interfacial issues compared with the commonly used gate- recess metal-insulator-semiconductor HEMTs. Thanks to the low-damage RPO treatment, the achieved E-mode HEMTs with threshold voltage of 0.4 V exhibit quite a small loss of output current (7.8%) compared with the depletion-mode devices. In addition, the AlON gate insulator layer results in a remarkable increase in breakdown voltage of devices from 20 V to 74 V, which benefits the high-voltage operation of AlN/GaN technology. Further investigation shows that the oxidation process of AlN barrier tends to be saturated with treatment time increasing, providing a promising solution to the high-performance E-mode operation of scaled GaN-based HEMTs in RF applications.

Selective sublimation of GaN and regrowth of AlGaN to co-integrate enhancement mode and depletion mode high electron mobility transistors

In the present study, the selective sublimation of the p-GaN cap layer of Al(Ga)N/GaN HEMTs is developed to replace the commonly used dry etching with no risk of damage in the barrier layer in order to fabricate enhanced mode transistors. Thanks to this approach, enhancement-mode transistors are fabricated with a threshold voltage between 0 V and +1.5 V depending on the barrier layer aluminum molar fraction and thickness. Furthermore, we show the benefit of the combination of selective sublimation with the regrowth of AlGaN to reduce access resistance in these transistors which can be co-integrated with depletion-mode devices fabricated in the same process in areas where p-GaN has been totally evaporated.

E-mode All-GaN-Integrated cascode MISHEMT with GaN/InAlGaN/GaN backbarrier for high power switching performance: Simulation study

In this work, simulation-based research work based on a novel All-GaN-Integrated Cascode (AGC) MISHEMT with quaternary layer InyAlxGa1-x-yN as backbarrier has been investigated. The AGC-MISHEMT device consists of series combination of enhancement mode (recessed gate MISHEMT) and depletion-mode (MIS-gate) GaN devices with GaN/InAlGaN/GaN sandwich back barrier (SW-BB). TCAD simulations indicate that AGC-MISHEMTs with sandwich back barrier (SW-BB) exhibits simultaneous improvement in terms of drain current density (267 ​mA/mm), high ION/IOFF ratio (108), transconductance-peak (191 ​mS/mm) and breakdown voltage (371 ​V) as compared to AGC-MISHEMT with GaN buffer. The impact of varying mole fractions (x, y), thickness and position of InyAlxGa1-x-yN layer on breakdown voltage has also been examined. Improvement in drain current density up to 40% has been accomplished with increased gate oxide thickness under gate 2 (depletion-mode device) for AGC-MISHEMT with SW-BB. Besides, power switching performance has been compared for AGC-MISHEMT with SW-BB to that of AGC-MISHEMT with GaN buffer and Recessed Single Gate (RSG) MISHEMT for inductive load circuit. Significant reduction in power switching losses (i.e. 43% during turn-ON time and 87% during turn-OFF time) has been observed for AGC-MISHEMT with SW-BB as compared to RSG-MISHEMT. In addition, introduction of quaternary InAlGaN layer in backbarrier for AGC-MISHEMT also results in considerable degradation (∼89%) in power loss when input gate is in OFF-state due to improved ION/IOFF ratio in contrast with recessed single gate device.

Combination of selective area sublimation of p-GaN and regrowth of AlGaN for the co-integration of enhancement mode and depletion mode high electron mobility transistors

We report on the fabrication of an enhancement mode p-GaN/AlN/GaN high electron mobility transistor with selective area sublimation under vacuum of the p-GaN cap layer. The GaN evaporation selectivity is demonstrated on the thin 2 nm AlN barrier layer. Furthermore, the regrowth of AlGaN is a major key to increase the maximum drain current in the transistors and enables the co-integration with depletion mode devices.

(Invited) AlGaN Transistors for Digital Logic Applications in High-Temperature Environments

Al-rich AlGaN HEMTs (high electron mobility transistors) are promising for extreme environment applications1. Over wide temperature ranges III-N HEMTs with ternary channels (AlGaN) exhibit more stable device behavior, compared to GaN, due to their alloy scattering-dominant transport, rather than the polar optical phonon scattering that dominates binaries (GaN). Additionally, Al(x>50%)Ga(1-x)N’s Ultra-Wide Band Gap enables superior suppression of intrinsic carrier density effects and thermionic emission-induced leakage2, making them prime candidates for high temperature electronics. While wide band gap (WBG) materials, such as SiC and GaN, have been previously investigated for high temperature device operability, the ultra-wide bandgap of Al-rich AlGaN potentially offers further advantages. We report on AlGaN logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature dependent carrier transport for different AlGaN compositions, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters.For the carrier transport characterization over temperature, Hall mobility data were collected for four different (Al)GaN HEMT structures with different Barrier/Channel AlxGa1-xN aluminum compositions. As the temperature increased from room temperature to 500°C, the GaN-channel HEMT experienced a 6.9× reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. A greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. For the gate metal scheme three stacks selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height were evaluated. HEMTs were fabricated on Al0.85Ga0.15N barrier / Al0.7Ga0.3N channel epitaxy and used a Ti/Al/Ni/Au Ohmic metal (annealed at 1100°C). The gate metal stacks evaluated were: (1) 20 nm Pt / 200 nm Au, (2) 200 nm Pd, and (3) 200 nm W. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal (500°C, 10 minutes, 1 mTorr nitrogen atmosphere). The 200 nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude improvement in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration. P. H. Carey, F. Ren, A. G. Baca, B. A. Klein, A. A. Allerman, A. M. Armstrong, E. A. Douglas, R. J. Kaplar, P. G. Kotula and S. J. Pearton, Journal of the Electron Devices Society 7, 444-452 (2019).P. G. Neudeck, R. S. Okojie and L.-Y. Chen, Proceedings of the IEEE 90 (6), 1065 - 1076 (2002). Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. SAND2021-4920 A

Multimode Operation of Organic-Inorganic Hybrid Thin-Film Transistors Based on Solution-Processed Indium Oxide Films.

Solution-processed metal oxide (MO) thin films have been extensively studied for use in thin-film transistors (TFTs) due to their high optical transparency, simplicity of fabrication methods, and high electron mobility. Here, we report, for the first time, the improvement of the electronic properties of solution-processed indium oxide (InOx) films by the subsequent addition of an organic p-type semiconductor material, here 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene), yielding organic-inorganic hybrid TFTs. The addition of TIPS-pentacene not only improves the electron mobility by enhancing the charge carrier percolation pathways but also improves the electronic and temporal stability of the IDS(VG) characteristics as well as reduces the number of required spin-coating steps of the InOx precursor solution. Very interestingly, the introduction of 10 nm TIPS-pentacene films on top of 15 nm InOx layers allows the fabrication of either enhancement- or depletion-mode devices with only minimal changes to the fabrication process. Specifically, we find that when the TIPS-pentacene layer is added on top of the source/drain electrodes, resulting in devices with embedded source/drain electrodes [embedded electrode TFTs (EETFTs)], the devices exhibit an enhancement-mode behavior with an average mobility (μ) of 6.4 cm2 V-1 s-1, a source-drain current ratio (Ion/Ioff) of around 105, and a near-zero threshold voltage (VTH). When on the other hand the TIPS-pentacene layer is added before the source-drain electrodes, i.e., in top-contact electrode TFTs (TCETFTs), a very clear depletion mode behavior is observed with an average μ of 6.3 cm2 V-1 s-1, an Ion/Ioff ratio of over 105, and a VTH of -80.3 V. Furthermore, a logic inverter is fabricated combining the enhancement (EETFTs)- and depletion (TCETFTs)-mode transistors, which shows a potential for the construction of organic-inorganic hybrid electronics and circuits.

An ultra‐fast protection scheme for normally‐on wide bandgap devices

Here, an ultra-fast protection scheme that is dedicated to depletion-mode (d-mode) devices is proposed. The key to the d-mode device gate drive design is the negative supply and overcurrent protection, due to the safety concern for d-mode devices when a failure happens in power conversion applications. This work evaluates specific requirement of d-mode devices, such as the isolated negative power supply and short-circuit protection. Normally-on d-mode GaN devices have lower on-resistance and minimal dead time in comparison with enhancement-mode (e-mode) GaN devices, which can further reduce the switching loss and conduction loss. Both simulation and experimental verification are conducted in this work to evaluate the performance of the proposed protection scheme. The proposed desaturation scheme can wipe out the overcurrent event within 341 ns. Furthermore, the proposed negative power supply scheme can sustain its output for 60.5 ms, providing sufficient action time for the control unit to isolate the converter.

Temperature Effect on Performance of Enhancement Mode Al0.4Ga0.6n-Channel Moshfets with Hybrid Oxide

The metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) based on AlxGa1-xN materials with the high aluminum composition is a promising choice for high-power, high-temperature harsh environment applications. In the present work the temperature stability of MOSHFETS with high-k ZrO2, Al2O3 gate dielectrics has been studied. Our data show these high-k dielectrics introduce negative fixed charges (Qox) as high as 1-3×1013 cm-2 depleting 2DEG density of 2×1013 cm-2 causing a positive shift of threshold voltage (VTH) compared to that for HFET which is an important feature for realizing enhanced (E-) mode MOSHFET. ZrO2 possesses higher Qox resulting in stronger positive VTH shift in devices, while devices with Al2O3 demonstrate lower gate leakage. To take advantages of both oxides, UWBG Al0.4Ga0.6N channel E-mode MOSHFET has been fabricated. E-mode device was realized using the hybrid oxide (ZrO2/Al2O3) combined with gate recess. To separate effects of dielectric charges and damage from recess process on device performance depletion (D-) mode and E-mode devices were fabricated on the same wafer simultaneously. D-mode devices were protected during gate recess step to avoid additional damage. Thermally induced VTH instability of these MOSHFETs were studied and potential mechanism for this VTH instability is discussed. Experimental: Figure 1(a) shows the pseudomorphic device structure that was grown using metalorganic chemical vapor deposition on AlN/sapphire templates. A graded composition (AlxGa1-xN, x=1-0.4) back barrier reduces internal stress and improves gate control in the devices.[i] , [ii] The top 200 Å thick graded n-AlxGa1-xN (x from 0.6 to 0.3) layer assists with the formation of ohmic contacts resistance as low as 1.7 Ω-mm. The n-doping of this layer compensates the positive charges resulting from the reverse composition grading.[iii] The 2DEG sheet resistance was ~1900 ohm/□. Device processing details published elsewhere.[iv] The fixed gate-length LG ≈ 2.0 μm, source to drain spacing, LSD=6 μm, were used for regular devices with 15 μm channel width, while for precise C(V,T,f) measurements we use a test structure with gate area 200x80 μm2 . Results and discussion: The combination of gate recessing and hybrid oxide resulted in threshold-voltage (VTH) shift of +12.2 V from D to E-mode device (Figure 1(b)). The gate leakage current in both D and E-mode MOSHFETs is ~103 smaller than that of MOSHFETs using singe Al2O3 or ZrO2 layer (Figure 2(a)) which allows us to apply gate voltage as high as +12 V. The peak DC currents for D and E-mode devices were found to be 1.1 A/mm and 0.48 A/mm respectively while in the pulse mode it was 1.3 A/mm and 0.53 A/mm. ON/OFF ratio as high as 3×108 was achieved which is higher than ~2 orders of magnitude than that for Al2O3 or ZrO2. We then performed temperature dependent threshold and gate leakage study of our fabricated MOSHFETs. Figure 2(b) shows the temperature dependent gate leakage characteristics of MOSHFETs of this study. It has been found that, in the D-mode MOSHFET, the VTH experiences positive VTH shift of + 1.7 V from RT to 150 °C; for the E-mode MOSHFET the shift is negative: -2.9 V (Figure 3(a)). The VTH shift for similar device having Schottky gate (no dielectric) (HFET) is significantly smaller, +0.2 V. This shows that the VTH shift is mainly due to the charges in dielectric or at dielectric-barrier interface. In the E-mode devices, the effective channel mobility and VTH was additionally affected by radiative defects introduced during gate-recess step. The mobility (µ) in D-mode devices decreases with temperature while it increases for the E-mode devices. We estimated temperature dependent interface state density (DIT(T)) and Qox (T) using frequency- dependent C-V measurements as shown in Figure 3(b). Our analysis show that in D-mode device, Qox(T) dominates over interface charges. These are fixed negative charges which deplete the channel giving a total VTH shift of +1.7 V from RT to 150°C. The extracted SS value for D and E-mode devices were 99 mV/decade and 134 mV/decade, indicating an increased density of interface traps (DIT) at the recessed interface in the E-mode device. Larger DIT value in E-mode devices caused by a radiation damage from the barrier recessing process and becomes comparable with Qox. Thus the temperature effect on Qox is compensated by DIT changes, increasing SS and making the VTH(T) more negative.[i]) G. Simin et al., Jpn. J. Appl. Phys., 40, L1142 (2001).[ii]) C. Ren et al., J. Semicond. 36, 014008-1 (2015).[iii]) S. Bajaj et al., Appl. Phys. Lett. 109, 133508-1 (2016).[iv]) S. Mollah et al., Appl. Phys. Lett. 117, 232105 (2020). Figure 1

Current Trends in the Development of Normally-OFF GaN-on-Si Power Transistors and Power Modules: A Review

Gallium nitride (GaN) power transistors have attracted significant interest in the power electronics industry over the past decade as the next-generation power semiconductor devices. GaN power transistors are suitable for high power and high frequency applications due to their higher electron mobility, temperature tolerance, electrical conductivity, critical breakdown electric field, and breakdown voltage compared to the conventional silicon-based transistors and other wide bandgap (WBG) power transistors. In particular, GaN-on-silicon (GaN-on-Si) technology has opened up the possibility of manufacturing high-performance, low-cost WBG power devices in silicon-compatible fabrication facilities. The first GaN power transistor structure to be developed was the normally-ON depletion mode (D-mode) device. It relies on the highly mobile two-dimension electron gas (2DEG) at the GaN/AlGaN epitaxial layers’ interface to provide very low on-resistance. The normally-OFF enhancement mode (E-mode) GaN power transistor soon became available by controlling the 2DEG using various gate structures. This paper provides a review of the developments of GaN power transistors followed by a survey on current state-of-the-art GaN power technologies and applications, including comparisons between GaN growth substrates and developments of enhancement mode (E-mode) device structures and their process techniques. Moreover, developments of power module designs are also addressed, including gate driver designs and their requirements, and packaging techniques for power transistors and power modules.

Organic Electrochemical Transistors Based on the Conjugated Polyelectrolyte PCPDTBT-SO3 K (CPE-K).

PCPDTBT-SO3 K (CPE-K), a conjugated polyelectrolyte, is presented as a mixed conductor material that can be used to fabricate high transconductance accumulation mode organic electrochemical transistors (OECTs). OECTs are utilized in a wide range of applications such as analyte detection, neural interfacing, impedance sensing, and neuromorphic computing. The use of interdigitated contacts to enable high transconductance in a relatively small device area in comparison to standard contacts is demonstrated. Such characteristics are highly desired in applications such as neural-activity sensing, where the device area must be minimized to reduce invasiveness. The physical and electrical properties of CPE-K are fully characterized to allow a direct comparison to other top performing OECT materials. CPE-K demonstrates an electrical performance that is among the best reported in the literature for OECT materials. In addition, CPE-K OECTs operate in the accumulation mode, which allows for much lower energy consumption in comparison to commonly used depletion mode devices.

The Development of a New Ion Versus Log(Ig) Plot to Characterize Depletion-Mode High Electron Mobility Transistors with the Insertion of a Very Thin Evaporated Al Layer to AlGaN/GaN High Electron Mobility Transistors as an Example

Previously, we showed that the Id_on vs. log Id_off plot can be used to characterize silicon-based enhancement-mode MOS transistors for both p-channel and n-channel [1]. AlGaN/GaN high electron mobility transistors (HEMTs) have attracted world-wide interest for microwave power transistor applications. There are two kinds of AlGaN/GaN HEMTs: depletion-mode and enhancement-mode AlGaN/GaN HEMTs. In general, depletion-mode AlGaN/GaN HEMTs are more common. For depletion-mode devices with the source at 0 V, even though the gate voltage may be close to zero, the gate leakage current increases with the increase of the drain voltage and can be significant because of a large drain voltage. Thus the gate leakage current may limit the maximum drain voltage and thus the RF power output of the device. For depletion-mode high electron mobility transistors (HEMTs), it can be easily imagined that both the on current (Ion) and the gate leakage current (Ig) will be increased by using a low work function metal as gate metal. Thus the drain on current (Id_on) and the gate leakage current (Ig) alone will not be a good criterion to judge the quality of depletion-mode HEMTs. In this paper, we would like to propose the application of a new Id_on vs. log Ig plot to characterize depletion-mode HEMTs. In the literature, a lot of various approaches have been proposed to cut down the gate leakage current. Recently, Nanjo et al. proposed to use a thin Al layer inserted between AlGaN and the Schottky metal gate to reduce the gate leakage current [2]. The advantage of this approach was subsequently confirmed by Selvaraj and Egawa [3]; however, they emphasized on the increase of the drain current instead of the reduction in the gate leakage current. It is natural to wonder how Al insertion can ever increase the drain current. Hence, the physics behind this approach is not yet clear. In this paper, we will also propose our theory regarding the physics of Al gate for AlGaN/GaN HEMT’s. With the help of this new plot, the superiority of the sample with Al/Ni/Au gate compared to the control sample with Ni/Au gate can be easily seen because the on current is higher for the same gate leakage current.As shown in Fig. 1, it can be easily shown that the Al insertion significantly improves the device for the same gate leakage current. According to theory, the Schottky barrier height φb is given by φb = φm - χs, where φm and χs are the metal work function and the electron affinity of the semiconductor. It is known that the work function of Al is significantly lower than that of Ni. It can be easily predicted that AlGaN/GaN HEMT with Al gate should have much larger gate leakage current compared to that with Ni gate. In fact, this was experimentally observed by us if the Al was evaporated rapidly during sample deposition. Our explanation of the advantage of Al insertion was that there was residual water vapor present in the vacuum chamber during electron beam evaporation [4]. According to Kordos et al. [5], the electron mobility of the 2-D electron gas at the AlGaN/GaN interface can be improved by a thin layer of Al2O3 on top of AlGaN/GaN. This experimental observation was also reported by Liu et al. [6]. It can be easily imagined that the presence of a thick layer of Al2O3 on top of AlGaN/GaN will degrade the performance of AlGaN/GaN HEMT because the distance between the metal gate and the AlGaN/GaN interface becomes bigger. However, when the thickness of the Al2O3 layer is small enough, the improvement of the electron mobility will be more significant than the degradation due to the increase of the distance between the metal gate and the AlGaN/GaN interface, resulting in the improved performance of the AlGaN/GaN HEMT.

Normally-Off-$\beta$ -Ga2O3 Power MOSFET With Ferroelectric Charge Storage Gate Stack Structure

In this work, we have demonstrated normally-off $\beta {-}\text {Ga}_{{2}}\text {O}_{{3}}$ metal-oxide-semiconductor field-effect transistor (MOSFET) with the ferroelectric charge storage gate stack structure. Saturation currents of 18.3 and 16.0 mA/mm were achieved in Depletion (D–) and Enhancement (E–) mode device, respectively, which shows negligible current reduction. Steep subthreshold swing (SS) of 72 mV/dec and breakdown voltage of 670 V were also obtained in the E-mode MOSFET. Furthermore, after gate stess test of 10 V for 105 s was performed, the threshold voltage $({V}_{\textit {TH}})$ shift was 26.5 %. These electrical characteristics of the E-mode $\beta {-}\text {Ga}_{{2}}\text {O}_{{3}}$ MOSFET shows the great potential for future power switch application.

Radiation-Induced DC Parametric Degradation of Enhancement Mode GaN-on-(111)Silicon High-Electron-Mobility Transistors

AlGaN/GaN high-electron-mobility transistors (HEMTs) for applications in radiation environments has required the exact determination of their radiation hardness. Although bulk GaN is the preferred substrate for the epitaxial growth of GaN and AlGaN, (111) silicon is a possible substrate for HEMT devices. The stability of electrical parameters of enhancement-mode (E-mode) GaN HEMTs under gamma irradiation is an essential characterization for reliability. The present work reports the transfer characteristics degradation of E-mode GaN HEMTs under various total dose irradiation from 5krad up to 60Mrads. This represents the first comprehensive total dose study ranging from a few krads up the tens of Mrads. The measured device-to-device variations within groups of devices are presented. The evolutions of critical DC parameters with accumulated total dose is found to be significant at low doses and saturates at high dose levels. The degradation mechanism is very similar to the reported radiation-induced shallow electron traps that trap and release electrons in the near surface GaN and AlGaN layers. Due to the unique properties including high breakdown voltage, high electron mobility and high thermal stability, wide-bandgap semiconductor power electronic devices, especially Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs), have shown great promise in space, defense and nuclear applications, which often involve radiation-hardened electronics that require high radiation tolerance to fluxes of neutrons or gamma ray of devices. To turn the promising potential of GaN HEMTs into reality, investigations on the influence of irradiation on the device performance and reliability are essential. Many studies have investigated the radiation hardness of group III–nitride compound semiconductor devices under various irradiation types, such as electrons, protons, neutrons, and X-rays and at various total irradiation doses. They generally showed higher radiation tolerance compared with Si because of high displacement energy of GaN, demonstrating the favorability of GaN devices in hard radiation environments. Many studies have investigated the influence of 60Co gamma radiation on the device electrical characteristics. However, they were all focusing on depletion mode (D-mode) devices. Enhancement mode (E-mode) GaN-on-Si transistors have been commercially available for years. Their major advantages over D-mode devices are elimination of negative voltage supply and the enabling of direct-coupled FET logic (DCFL) for digital circuits. They also improve the efficiency of commercial DC-DC converters in various power levels and topologies. A previous work on gamma radiation of E-mode GaN-on-Si HEMTs only reported cumulative total doses of up to 1 Mrads (Si). The present work provides a complete coverage of low-to-high irradiation doses from 5krads up to 60Mrads (Si), for commercially available E-mode GaN HEMTs and the devices are characterized to gauge variations in the critical DC parameters. To the best of the author’s knowledge, the present work is the first to investigate the gamma radiation tolerance of E-mode GaN HEMTs covering such a wide range of total doses. This facilitates the observation of the complete degradation behavior of DC parameters in hard radiation applications of the E-mode GaN HEMTs. The devices were supplied in the form of 0.9mm square passivated die with round solder bumps for contacts. They have a rated continuous drain-to-source voltage VDS of 60V, and a rated continuous drain current ID of 1A. These GaN-on-Si devices were fabricated on Si wafers considering process compatibility and cost. An aluminum nitride (AlN) thin layer was grown on the Si wafer to be a seed layer for the AlGaN/GaN heterostructure. Subsequently, the AlGaN/GaN heterostructure was grown on the AlN layer, with a thin AlGaN layer grown above the highly resistive GaN serving as a strained interface between the GaN and AlGaN crystal layers, allowing the creation of a two-dimensional electron gas (2DEG) filled with abundant free electrons with ultra-high mobility. The gate electrode was processed subsequently forming a depletion region under the gate. As an E-mode transistor, the device is turned on by applying a positive bias to the gate. All the irradiations were conducted at room temperature by 60Co gamma-rays with a flux of 318.5Rads (Si)/s, at the dry-cell panoramic gamma irradiator in the University of Maryland Radiation Facilities. The entire irradiation procedure consists of two parts. The first part is higher-dose irradiation with total doses of up to 60Mrads based on two stages. At the first stage, the devices were irradiated at 10Mrads, while at the second stage, the devices were irradiated for another 50Mrads, with three of them taken out after 25Mrads during the second stage. The second part is lower-dose irradiations with total doses of up to 2Mrads. The temperature throughout the irradiation process was monitored to be below 30°C.

Turn-off mechanisms in thin-film source-gated transistors with applications to power devices and rectification

We describe the physics of the turn-off mechanism in source-gated transistors (SGTs), which is distinct from that of conventional thin-film field-effect transistors and allows significantly lower off currents, particularly in depletion-mode devices. The “n-type” SGT enters its off state when the potential applied across the semiconductor layer is decreased to low positive values or made negative through the applied gate bias, thus impeding charge injection from the source contact. Measurements on polysilicon devices were supported with TCAD simulations using Silvaco Atlas. Alongside the other known benefits of SGTs, including low saturation voltage, tolerance to process variations, and high intrinsic gain, the ability to efficiently block current at high negative gate voltages suggests that these devices would be ideal elements in emerging thin-film power management and rectification circuits.

Enhancement-mode Al0.85Ga0.15N/Al0.7Ga0.3N high electron mobility transistor with fluorine treatment

Enhancement-mode Al0.7Ga0.3N-channel high electron mobility transistors (HEMTs) were achieved through a combination of recessed etching and fluorine ion deposition to shift the threshold voltage (VTH) relative to depletion-mode devices by +5.6 V to VTH = +0.5 V. Accounting for the threshold voltage shift (ΔVTH), current densities of approximately 30 to 35 mA/mm and transconductance values of 13 mS/mm were achieved for both the control and enhancement mode devices at gate biases of 1 V and 6.6 V, respectively. Little hysteresis was observed for all devices, with voltage offsets of 20 mV at drain currents of 1.0 × 10−3 mA/mm. Enhancement-mode devices exhibited slightly higher turn-on voltages (+0.38 V) for forward bias gate currents. Piecewise evaluation of a threshold voltage model indicated a ΔVTH of +3.3 V due to a gate recess etching of 12 nm and an additional +2.3 V shift due to fluorine ions near the AlGaN surface.

Effect of HCl cleaning on InSb–Al2O3 MOS capacitors

In this work, the role of HCl treatments on InSb surfaces and InSb–Al2O3 dielectric interfaces is characterised. X-ray photoelectron spectroscopy measurements indicate that HCl diluted in and rinsed with isopropanol (IPA) results in a surface layer of InCl3 which is not present for similar HCl-water processes. Furthermore, this InCl3 layer desorbs from the surface between 200 °C and 250 °C. Metal–oxide–semiconductor capacitors were fabricated using atomic layer deposition of Al2O3 at 200 °C and 250 °C and the presence of InCl3 was associated with a +0.79 V flatband voltage shift. The desorption of the InCl3 layer at 250 °C reversed this shift but the increased process temperature resulted in increased interface-trapped charge (D it) and hysteresis voltage (V H ). This shift in flatband voltage, which does not affect other figures of merit, offers a promising route to manipulate the threshold voltage of MOS transistors, allowing enhancement-mode and depletion-mode devices to be fabricated in parallel.

Inverter Logic of AlGaAs/InGaAs Enhancement/Depletion-Mode Pseudomorphic High Electron Mobility Transistors with Virtual Channel Layers

In this article, the direct-coupled FET logic (DCFL) inverters are implemented by co-integrated AlGaAs/InGaAs depletion-mode and enhancement-mode pseudomorphic high electron mobility transistors with virtual channel layers, and the inverters with varying gate width of the depletion-mode transistors are demonstrated. The experimental results show that the drain current IDS (mA/mm) and gm (mS/mm) per unit gate width increases as the gate widths of the depletion-mode devices decrease. This is attributed to the fact that the drain current and transconductance values are related to the channel-to-source resistance and the source contact resistance. When the gate width is reduced, the source pad contact area is only slightly changed and the IDS (mA/mm) as well as the transconductance gm (mS/mm) will increase. In addition, it is also observed that for the reduce of the gate width of the depletion-mode devices, the transfer characteristics of the DCFL inverters are steep and shift to the left due to the smaller drain saturation current of the load transistor.