Depletion-load Inverter Research Articles

Reversible Carrier Concentration Control on Ultra-Thin in2O3 By Viologen Molecules Charge Transfer Method

Ultra-thin Oxide semiconductor fabricated by atomic layer deposition (ALD) is one of the promising candidates, due to their ultra-thin thickness and being highly compatible with the silicon process.[1] However, further tuning the oxide semiconductor's carrier concentration is still an interesting issue. Although annealing is a widely used way, the increase in thermal budget is unwilling to be met. To adjust the carrier concentration without increasing the thermal budget, viologen molecule, a strongly n-type dopant which have been successfully applied to different material systems including 2D,[2] CNT,[3] ultra-thin Ⅲ-Ⅴ,[4] has been used in the In2O3 transistor(as shown in Figure 1a). After viologen treatment, the viologen dopants increased the carrier concentration and caused a difference of n 2D, which is 2 × 1012 cm-2 of 2 nm thickness in In2O3, without degrading the mobility under the same overdrive voltage. The In2O3 transistor achieves an electron sheet density of 6.8 × 1012 cm−2. To further expand the function, viologen dopants are modified by hydroxy group. With hydroxy group modifying, the viologen dopants can be removed by acetone and be re-treated back on the In2O3 again. The reversible cycle of viologen treatment can be repeated multiple times without harming the In2O3 device (as shown in Figure 1b). Precise control of the threshold voltage allows for fine-tuning of the transistor between depletion mode and enhancement mode. Based on this, a depletion load inverter has been demonstrated. This result shows that the viologen dopants and In2O3 have the potential to be further integrated with other low dimensional materials in BEOL without raising the thermal budget while tuning the carrier concentrations. Figure 1. a) Schematic representation of the structure of a In2O3 bottom-gate transistor and the viologen charge transfer process. b) The transfer characteristics of In2O3 transistors repeatedly treated and removed of OHV for four cycles. References (1) Si, M.; Lin, Z.; Chen, Z.; Sun, X.; Wang, H.; Ye, P. D. Scaled Indium Oxide Transistors Fabricated Using Atomic Layer Deposition. Nat. Electron. 2022, 5 (3), 164-170. DOI: 10.1038/s41928-022-00718-w.(2) Kiriya, D.; Tosun, M.; Zhao, P.; Kang, J. S.; Javey, A. Air-Stable Surface Charge Transfer Doping of MoS2 by Benzyl Viologen. J. Am. Chem. Soc. 2014, 136 (22), 7853-7856. DOI: 10.1021/ja5033327.(3)Kim, S. M.; Jang, J. H.; Kim, K. K.; Park, H. K.; Bae, J. J.; Yu, W. J.; Lee, I. H.; Kim, G.; Loc, D. D.; Kim, U. J.; Lee, E.-H.; Shin, H.-J.; Choi, J.-Y.; Lee, Y. H. Reduction-Controlled Viologen in Bisolvent as an Environmentally Stable n-Type Dopant for Carbon Nanotubes. J. Am. Chem. Soc. 2009, 131 (1), 327-331. DOI: 10.1021/ja807480g.(4) Takei, K.; Kapadia, R.; Li, Y.; Plis, E.; Krishna, S.; Javey, A. Surface Charge Transfer Doping of III–V Nanostructures. J. Phys. Chem. C 2013, 117 (34), 17845-17849. Figure 1

Wide-range and area-selective threshold voltage tunability in ultrathin indium oxide transistors

The scaling of transistors with thinner channel thicknesses has led to a surge in research on two-dimensional (2D) and quasi-2D semiconductors. However, modulating the threshold voltage (VT) in ultrathin transistors is challenging, as traditional doping methods are not readily applicable. In this work, we introduce a optical-thermal method, combining ultraviolet (UV) illumination and oxygen annealing, to achieve broad-range VT tunability in ultrathin In2O3. This method can achieve both positive and negative VT tuning and is reversible. The modulation of sheet carrier density, which corresponds to VT shift, is comparable to that obtained using other doping and capacitive charging techniques in other ultrathin transistors, including 2D semiconductors. With the controllability of VT, we successfully demonstrate the realization of depletion-load inverter and multi-state logic devices, as well as wafer-scale VT modulation via an automated laser system, showcasing its potential for low-power circuit design and non-von Neumann computing applications.

All‐Solid‐State Organic Schmitt Trigger Implemented by Twin Two‐in‐One Ferroelectric Memory Transistors

AbstractAlthough there have been many attempts to replace conventional inorganic electronics with organic materials that can be mass produced at low cost, few organic electronic filters to increase immunity to electrical noise have been reported thus far. Conventional Schmitt triggers or their inverters are used in many electronic circuits as versatile electronic noise filters. However, it is challenging to manufacture organic electronic systems with complex circuitry. In this study, a simple, all‐solid‐state organic Schmitt trigger consisting of twin two‐in‐one organic ferroelectric memory transistors with the same chemical compositions and device dimensions but different threshold voltages is introduced. Threshold voltages and hysteresis in the two‐in‐one devices can be controlled by polarization switching as demonstrated in a previous study. Hysteresis of a ferroelectric p‐type depletion load inverter can be achieved using twin two‐in‐one devices when the sweep voltage is higher than the critical gate voltages. This facilitates inverter characteristics at two different threshold voltages, and realizing a Schmitt trigger. Finally, based on simulation program with integrated circuit emphasis (SPICE) simulation, guidelines are proposed on how to design organic Schmitt triggers with p‐ or n‐type materials and ferroelectric or charge‐trapping mechanisms to achieve inverting or non‐inverting characteristics.

Low-Voltage Depletion-Load Inverter Using Solid-State Electrolyte Gated Oxide Transistors

A low-voltage depletion-load inverter consisting of oxide transistors gated by nanogranular phosphorosilicate glass electrolytes has been fabricated. An indium-zinc-oxide electric-double-layer (EDL) transistor shows a threshold voltage (Vth) of approximately -0.1 V and acts as a load. An indium-gallium- zinc-oxide EDL transistor shows a Vth of ~0.3 V and acts as a driver. The depletion-load inverter shows a high voltage gain of 40 and a narrow transition width of <;0.2 V at low supply voltage of 2 V. The proposed low-voltage inverter may find potential applications in portable electronics and biosensors.

1-V Full-Swing Depletion-Load a-In–Ga–Zn–O Inverters for Back-End-of-Line Compatible 3D Integration

To enable monolithic three-dimensional integration of the amorphous In–Ga–Zn–O (a-IGZO) and CMOS technologies, the a-IGZO inverters compatible with the low operating voltage ( $\leqq 1$ V) and process temperature of back-end-of-line CMOS have been investigated. We demonstrated a full-swing depletion-load inverter with a voltage gain up to 24 using a CMOS-compatible operating voltage of 1 V. The drive transistor was realized using a low-voltage enhancement-mode a-IGZO thin-film transistor (TFT) with a steep subthreshold swing of 70 mV/decade and a low threshold voltage of 0.5 V. The load transistor was implemented using a bi-layer a-IGZO channel, where the a-IGZO composition was modulated simply by the oxygen flow rate in a depletion-mode TFT.

Versatile threshold voltage control of OTFTs via discontinuous pn-heterojunction formation

We demonstrate the versatility of the threshold voltage control for organic thin-film transistors (OTFTs) based on formation of discontinuous pn-heterojunction on the active channel layer. By depositing n-type dioctyl perylene tetracarboxylic diimide molecules discontinuously onto base p-type pentacene thin films (the formation of the discontinuous pn-heterojunction), a positive shift of the threshold voltage was attained which enabled realizing a depletion-mode transistor from an original enhancement-mode pristine pentacene transistor. Careful control of the threshold voltage based on this method led assembling a depletion-load inverter comprising a depletion-mode transistor and an enhancement-mode transistor connected in series that yielded tunable signal inversion voltage approaching 0V. In addition, the tunability could be applied to improve the program/erase signal ratio for non-volatile transistor memories by more than 4 orders of magnitude compared to reference memory devices made of pristine pentacene transistors.

Unipolar depletion-load organic circuits on flexible substrate by self-organized polymer blending with 6, 13-bis(triisopropylsilylethynyl)pentacene using ink-jet printing

We report the threshold voltage control and its application to electronic circuits of ink-jet printed organic thin-film transistors (OTFTs) with self-organized process using 6, 13-bis(triisopropylsilyl-ethynyl)pentacene (TIPS-pentacene) and insulating polymer on plastic substrate. The threshold voltage of OTFTs can be changed by using different polymer blending. The enhancement and depletion-mode OTFTs can be achieved, respectively, by using polystyrene and poly(vinylphenol) through self-organized blending on the common substrate. A unipolar depletion-load inverter composed of enhancement-mode driver and depletion-mode load OTFTs has been demonstrated with ink-jet printed TIPS-pentacene layer on both TFT channels. An inverter on plastic shows a gain of −90.8 V/V at the driving voltage of −2 V.

Low-Voltage Organic Transistors and Depletion-Load Inverters With High-K Pyrochlore BZN Gate Dielectric on Polymer Substrate

Pentacene organic thin-film transistors (OTFTs) have demonstrated the highest performance among TFTs with an organic semiconductor channel. High operating voltages (20-100 V), stemming from poor capacitive coupling between gate electrode and channel, are a major limitation, particularly for portable battery-powered device applications. OTFTs fabricated on flexible polymer substrates, often characterized by rough surfaces, benefit from the use of high-K dielectrics given the ability to accommodate thicker films which ensure the pinhole-free and good coverage without need to increase operating voltage. As we demonstrate, pyrochlore structured thin films can provide the requisite high dielectric constant coupled with excellent leakage current characteristics, while remaining compatible with the processing requirements of flexible OTFTs. The introduction of an extremely thin parylene film between the BZN dielectric and the pentacene semiconductor markedly shifts the threshold voltage, making it possible to fabricate both enhancement (E) and depletion (D) TFTs. We report the successful fabrication of low-voltage (<2 V) organic transistors and depletion-load inverter using a 200-nm-thick pyrochlore gate dielectric, Bi/sub 1.5/Zn/sub 1.0/Nb/sub 1.5/O/sub 7/ (BZN), prepared by a room temperature process. The inverters with depletion load were successfully operated under 5 V with excellent noise margin.

Delay-time evaluation in ED MOS logic LSI

An explicit formulation of the transient response of ED MOS logic gates is presented, including load conditions and driving waveforms. Defining delays as the time required by the current imbalance of the active inverter to charge or discharge the output load, with respect to physical reference levels, rise and fall mode delay times are obtained in an explicit formulation, with separate contributions due to fan-out and fan-in. Results are applied to ring oscillators and to depletion-load inverter chains with different configuration ratio values and are compared with SPICE simulations. With good agreement obtained, optimal structures with a low value of the configuration ratio can be defined. Analysis of propagation delay times in NOR, NAND, and transmission gates is given, allowing easy implementation of this model into logic simulators.

Harmonic performance of single-channel MOS integrated circuits

Using simple square-law models for both the MOSFET current-voltage characteristics and the relationship between the threshold voltage and the source-to-substrate voltage, simple expressions are presented for predicting the performance of the basic MOSFET circuits used in analog MOS technology. Using these expressions, the low-frequency gain and the second and third harmonic distortion performance of the enhancement-load inverters, enhancement-load source follower, depletion-load inverter, and depletion-load source follower can be easily predicted by hand calculations. The results obtained by using these expressions are compared with previously published measurements and calculations.

Harmonic distortion in single-channel MOS integrated circuits

Expressions assuming a simple square-law MOSFET model are presented for the low-frequency harmonic distortion of an enhancement-mode source follower. These theoretical results are compared to measurements of several integrated versions of the three circuit types. For a given fabrication process, the main factors determining the amount of distortion for all three circuits are the quiescent output voltage and the output swing; to a first order, the distortion does not depend on bias current or device geometries. The distortion of an enhancement-mode source follower has a similar behavior to that of an enhancement-load inverter with the same output quiescent voltage and output swing; both distortions are nearly proportional to the body-effect coefficient. For the same output quiescent voltage and output swing, the distortion of the depletion-load inverter is the highest among the three circuits, but is practically independent of process parameters.

Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systems

Minimization of the delay times associated with driving and sensing signals from large capacitance paths by optimizing the fan-out factor of the driver stages, the gain of the input sensing stages, and the path voltage swing are examined. Examples of driving signals on a high capacitance path with two driving schemes are: a push-pull depletion-load driver chain and a fixed driver; and of sensing signals with two sensing schemes: a single-ended depletion-load inverter input stage and a balanced regenerative strobed latch are presented.

Delay-time optimization for driving and sensing of signals on high-capacitance paths of VLSI systems

Transmission of signals on large capacitance paths in a VLSI system may result in substantial degradation of the overall system performance. In this paper minimization of the delay times associated with driving and sensing signals from large capacitance paths by optimizing the fan-out factor of the driver stages, the gain of the input sensing stages, and the path voltage swing are examined. Examples of driving signals on a high capacitance path with two driving schemes are: a push-pull depletion-load driver chain and a fixed driver; and of sensing signals with two sensing schemes: a single-ended depletion-load inverter input stage and a balanced regenerative strobed latch are presented. We conclude that minimum delay time is achieved when the delay times of the successive stages of the driver chain, the high capacitance path, and the input sensing stage are comparable. In general, transmission time of signals in a system is minimized when the delay times of the different stages of the system are comparable.

A high-performance N-channel MOSLSI using depletion-type load elements

A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.