Memory Density Research Articles

Designing current-strain-assisted superconductor-ferromagnet multi-bit memories

Current superconducting memory devices lack the basic quality of high memory density for practical memories, mainly due to the size limitations of superconducting quantum interference devices. Here, we propose a superconductor–ferromagnet bilayer device with strain-pulse-assisted multi-bit ladder-type memory, by using strain-engineered ferromagnet domain structure to control carrier concentration in the superconductor, which is simulated by coupled Landau–Lifshitz–Gilbert and Ginzburg–Landau equations. Current- and strain-pulses are observed to deterministically control the resistivity of superconductor for one and two-bit device arrangements. The average carrier concentration of superconductor is observed to have multiple metastable states that can be controllably switched using current-pulse and strain-pulse to determine multiple resistivity states. These findings confirm the eligibility of superconductor–ferromagnet bilayers to be used as ladder-type multibit memories and open a new way for further theoretical and experimental investigations of the cryogenic memories.

VIDEO-BASED TABLE TENNIS TRACKING AND TRAJECTORY PREDICTION USING CONVOLUTIONAL NEURAL NETWORKS

One of the fascinating aspects of sports rivalry is that anything can happen. The significant difficulty is that computer-aided systems must address how to record and analyze many game events, and fractal AI plays an essential role in dealing with complex structures, allowing effective solutions. In table tennis, we primarily concentrate on two issues: ball tracking and trajectory prediction. Based on these two components, we can get ball parameters such as velocity and spin, perform data analysis, and even create a ping-pong robot application based on fractals. However, most existing systems rely on a traditional method based on physical analysis and a non-machine learning tracking algorithm, which can be complex and inflexible. As mentioned earlier, to overcome the problem, we proposed an automatic table tennis-aided system based on fractal AI that allows solving complex issues and high structural complexity of object tracking and trajectory prediction. For object tracking, our proposed algorithm is based on structured output Convolutional Neural Network (CNN) based on deep learning approaches and a trajectory prediction model based on Long Short-Term Memory (LSTM) and Mixture Density Networks (MDN). These models are intuitive and straightforward and can be optimized by training iteratively on a large amount of data. Moreover, we construct a table tennis auxiliary system based on these models currently in practice.

APOE4 homozygote females are resistant to the beneficial effects of 17β-estradiol on memory and CA1 dendritic spine density in the EFAD mouse model of Alzheimer's disease

Female APOE4 carriers are at greatest risk of Alzheimer's disease (AD). The potent estrogen 17β-estradiol (E2) may mediate AD risk, as the onset of memory decline coincides with the menopausal transition. Whether APOE genotype mediates E2’s effects on memory and neuronal morphology is poorly understood. We used the APOE+/+/5xFAD+/- (EFAD) mouse model to examine how APOE3 homozygote (E3FAD), APOE3/4 heterozygote (E3/4FAD), and APOE4 homozygote (E4FAD) genotypes modulate effects of E2 on object and spatial memory consolidation, dendritic spine density, and dorsal hippocampal estrogen receptor expression in 6-month-old ovariectomized EFAD mice. Dorsal hippocampal E2 infusion enhanced memory consolidation and increased CA1 apical spine density in E3FAD and E3/4FAD, but not E4FAD, mice. CA1 basal mushroom spines were also increased by E2 in E3FADs. E4FAD mice exhibited reduced CA1 and mPFC basal spine density, and increased dorsal hippocampal ERα protein, independent of E2. Overall, E2 benefitted hippocampal memory and structural plasticity in females bearing one or no APOE4 allele, whereas two APOE4 alleles impeded the memory-enhancing and spinogenic effects of E2.

Quantum fluctuations in the order parameter of quantum skyrmion crystals

Traditionally, skyrmions are treated as continuum magnetic textures of classical spins with a well-defined topological skyrmion number. Owing to their topological protection, skyrmions have attracted great interest as building blocks in future memory technology. Smaller skyrmions offer greater memory density, however, quantum effects are not negligible for skyrmions with sizes of just a few lattice constants. In this paper we study quantum fluctuations around dense skyrmion crystal ground states, and focus on the utility of a discretized order parameter for quantum skyrmions. The order parameter is found to be a useful indicator of the existence of quantum skyrmions, and captures the quantum phase transition between two distinct skyrmion phases.

Abstract 2580: Infiltration and spatial distribution of immune cells are associated clinical benefit from Nivolumab and Ipilimumab for previously treated patients with stage IV squamous cell lung cancer: an immune biomarker analysis of Phase III SWOG LungMAP S1400I trial

Abstract Background: Lung squamous cell carcinoma (SCC) is the second most common type of non-small cell lung cancer. Immunotherapy is a promising treatment for SCC. However, only a small proportion of unselected SCC patients are able to achieve durable clinical benefit. We leveraged the precious specimens from S1400I trial and sought to explore whether the levels and spatial distributions of tumor-associated immune cells (TAICs) in screening samples are associated with PFS, and OS. Methods: We utilized paraffin tumor tissue provided by the SWOG bank from screening on LungMAP. 82/252 eligible SCC sample from patients treated with nivolumab plus ipilimumab (nivo+ipi; n = 35) or with nivolumab alone (nivo; n = 47) were studied. Image analysis tissue immunoprofiling was conducted using 9 markers in 2 multiplex immunofluorescence panels against cytokeratin, CD3, CD8, granzyme B, CD45RO, and FOXP3, PD1, PD-L1, and CD68. Densities of cells phenotypes (cells/mm2) were assessed and dichotomized as being high (> median) or low (≤ median) in tumor, stroma, and total compartments. Distances from malignant cells (MCs) to cell populations were measured and dichotomized as close from MCs (≤ median) and faraway from MCs (> median) and associated with clinical variables. Clinicopathologic features and data on PFS, and OS were retrieved from the CIDC portal as provided by the LungMap team. Non-parametric tests where utilized to assessment associations of cell phenotypes versus continue or categorical variables and log-rank test for survival analysis. Results: Univariate analysis showed that higher densities of memory T cells in total compartment (HR:0.63, CI:0.40-1.00, P=0.041), antigen-experienced T cells in the stroma (HR:0.60, CI:0.37-0.96, P=0.024) and total compartment (HR:0.60, CI:0.38-0.95, P=0.023) and activated cytotoxic T cells in the tumor compartment (HR:0.55, CI:0.35-0.87, P=0.011) were associated with significative better PFS. In the nivo+ipi arm, higher ratios of cytotoxic T cells to regulatory T cells in the stroma were associated with better PFS. The spatial analysis of these TAICs showed that the presence of activated cytotoxic T cells close to the MCs (median, ≤19.27 µm) was associated with better PFS (P=0.037). Conclusions: Our findings suggest that patients who have a detectable immunosuppressive tumor axis (PD-L1/PD1) with adequate activated cytotoxic T cells close to the tumor cells are the ideal patients for immune therapy to be targetable with these types of treatments. Acknowledgments: Scientific and financial support for: U10CA180888, U10CA180819U24CA224285, U24CA224316, PACT, PPP and FNIH. Citation Format: Edwin Roger Parra, Jiexin Zhang, Mary Redman, Rossana Lazcano, Piubelli Mario, Caddie Laberiano Fernandez, Renganayaki K. Krishna, Shanyu Zhang, Hong Chen, Ganiraju Manyam, Radim Moravec, Ethan Cerami, James Lindsay, Joyce Yu, Roshni Biswas, Stephen Van Nostrand, Dzifa Y. Duose, Jianjun Zhang, Roy Herbst, Gheath Al-Atrash, Kasthuri Kannan, Ignacio I. Wistuba, Scott Gettinger, Lyudmila Bazhenova, Jack Lee, Jianhua Zhang, Cara Haymaker. Infiltration and spatial distribution of immune cells are associated clinical benefit from Nivolumab and Ipilimumab for previously treated patients with stage IV squamous cell lung cancer: an immune biomarker analysis of Phase III SWOG LungMAP S1400I trial [abstract]. In: Proceedings of the American Association for Cancer Research Annual Meeting 2022; 2022 Apr 8-13. Philadelphia (PA): AACR; Cancer Res 2022;82(12_Suppl):Abstract nr 2580.

Androgens Enhance Recognition Memory and Dendritic Spine Density in the Hippocampus and Prefrontal Cortex of Ovariectomized Female Rats

Estrogen replacement has been repeatedly shown to enhance memory and increase dendritic spine density in the hippocampus and prefrontal cortex of ovariectomized (OVX) female rats. Given the potential deleterious effects of chronic estrogen administration, the present study assessed cognitive function using recognition memory tasks and measured dendritic spine density in the CA1 region of the hippocampus and medial prefrontal cortex after subchronic androgen replacement to adult OVX female rats. All androgens enhanced recognition memory in OVX rats, but object placement (OP) and object recognition (OR) results differed. Only testosterone enhanced OR. Testosterone had no effect on OP while dehydroepiandrosterone (DHEA), dihydrotestosterone (DHT) and androstenedione (AD) enhanced OP. Dendritic spine density was increased by both TP and DHEA in both brain areas (DHT and AD were not tested). Lastly, we used the aromatase inhibitor, letrozole, to discriminate between potential androgenic and estrogenic effects of androgens on behavior. Letrozole alone did not alter recognition memory in OVX rats and did not block the effects of either TP or DHEA on recognition memory suggesting that effects were mediated via androgenic mechanisms. The present results expand previous information on gonadal hormone actions and show that, in addition to estrogens, androgens also improve memory and increase spine density in brains of OVX female rats. While requiring further investigation, these observations provide a basis for therapeutic interventions in the treatment of menopausal, age or disease related memory loss.

ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM

Advances in the density and capacity of dynamic random access memories (DRAMs) have resulted in emerging reliability issues. The error correction code (ECC) is widely used as a promising technique to improve the reliability of high-density memories. For this reason, many studies on ECC have been conducted to address the increased cell failure rates. However, conventional ECCs have shown limited achievements owing to area, latency, and power overheads. This study proposes ECC architecture reusing content-addressable memories (CAMs) for obtaining high reliability in DRAM, which can be called ECMO. The proposed architecture reuses CAMs in built-in self-repair, which can be used to repair memory hard faults during manufacturing as data storage to replace error data words. This achieves high reliability along with an additional 9155 h DRAM lifetime. Nevertheless, it can be implemented with a 3.04% area overhead due to the reuse of CAMs. Moreover, only 0.21 ns is added to the critical path. Furthermore, the power overhead is 0.1% compared to the total power consumption of DDR3 and DDR4.

Ferroelectric Memory Based on Topological Domain Structures: A Phase Field Simulation

The low storage density of ferroelectric thin film memory currently limits the further application of ferroelectric memory. Topologies based on controllable ferroelectric domain structures offer opportunities to develop microelectronic devices such as high-density memories. This study uses ferroelectric topology domains in a ferroelectric field-effect transistor (FeFET) structure for memory. The electrical behavior of FeFET and its flip properties under strain and electric fields are investigated using a phase-field model combined with the device equations of field-effect transistors. When the dimensionless electric field changes from −0.10 to 0.10, the memory window drops from 2.49 V to 0.6 V and the on-state current drops from 2.511 mA to 1.951 mA; the off-state current grows from 1.532 mA to 1.877 mA. External tensile stress increases the memory window and off-state current, while compressive stress decreases it. This study shows that a ferroelectric topology can be used as memory and could significantly increase the storage density of ferroelectric memory.

Novel, parallel and differential synaptic architecture based on NAND flash memory for high-density and highly-reliable binary neural networks

A novel synaptic architecture based on a NAND flash memory structure is proposed as a high-density synapse capable of exclusive NOR (XNOR) operation for binary neural networks (BNNs). For the first time, a 4T2S-based synaptic architecture with a complementary input voltage that implements an equivalent bitwise XNOR operation is proposed. Two adjacent NAND flash strings connected with the word lines are used as one synaptic string with four input transistors connected to the bit-line. By changing the threshold voltage of the NAND flash cells and input voltages in a complementary fashion, the XNOR operation is successfully demonstrated. The large on/off current ratio (∼7 × 105) of the NAND flash cells and differential sensing scheme can implement high-density and highly reliable binary neural networks without error correcting codes (ECC), which can reduce the burden of the complementary metal–oxide–semiconductor (CMOS) overhead. Despite the string structure of NAND flash memory, the parallel read scheme significantly reduces the read-out latency when compared to the sequential read scheme. In addition, we show that with only 1 erase/program pulse, sufficiently low bit-error rate (7.6 × 10−9 %) is achieved without the conventional incremental step pulse programming (ISPP) scheme. Finally, the estimated synapse density of V-NAND flash memory with 128 stacks is ∼103 times that of the 2T2R synapse in resistive random access memory (RRAM).

Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems

Deep neural networks generate and process large volumes of data, posing challenges for low-resource embedded systems. In-memory computing has been demonstrated as an efficient computing infrastructure and shows promise for embedded AI applications. Among newly-researched memory technologies, racetrack memory is a non-volatile technology that allows high data density fabrication, making it a good fit for in-memory computing. However, integrating in-memory arithmetic circuits with memory cells affects both the memory density and power efficiency. It remains challenging to build efficient in-memory arithmetic circuits on racetrack memory within area and energy constraints. To this end, we present an efficient in-memory convolutional neural network (CNN) accelerator optimized for use with racetrack memory. We design a series of fundamental arithmetic circuits as in-memory computing cells suited for multiply-and-accumulate operations. Moreover, we explore the design space of racetrack memory based systems and CNN model architectures, employing co-design to improve the efficiency and performance of performing CNN inference in racetrack memory while maintaining model accuracy. Our designed circuits and model-system co-optimization strategies achieve a small memory bank area with significant improvements in energy and performance for racetrack memory based embedded systems.

C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.

Optimizing the thickness of Ta2O5 interfacial barrier layer to limit the oxidization of Ta ohmic interface and ZrO2 switching layer for multilevel data storage

• Optimization of the thickness (0, ∼ 2, ∼ 4, and ∼ 6 nm) of the Ta 2 O 5 interfacial barrier layer has been utilized to limit the oxidization of the Ta ohmic interface and ZrO 2 RS layer. • Lower forming/SET-voltages high pulse endurance (10 6 cycles), long retention time (10 4 s) at 100 °C, and reliable multilevel resistance states were obtained. • Multilevel resistance states have been scientifically investigated via modulating the compliance current (CC) and RESET-stop voltages. • I-V characteristics of HRS are found to be a good linear fit with the Schottky equation. • Schottky barrier height rises by increasing the stop-voltage during RESET-operation, resulting in enhancing the data storage memory window (on/off ratio). The multilevel storage capability of nonvolatile resistive random access memory (ReRAM) is greatly desired to accomplish high functioning memory density. In this study, Ta 2 O 5 thin film with different thicknesses (2, 4, and 6 nm) was exploited as an appropriate interfacial barrier layer for limiting the formation of the interfacial layer between the 10 nm thick sputtering deposited resistive switching (RS) layer and Ta ohmic electrode to improve the switching cycle endurance and uniformity. Results show that lower forming voltage, narrow distribution of SET-voltages, good dc switching cycles (10 3 ), high pulse endurance (10 6 cycles), long retention time (10 4 s at room temperature and 100°C), and reliable multilevel resistance states were obtained at an appropriate thickness of ∼2 nm Ta 2 O 5 interfacial barrier layer instead of without Ta 2 O 5 and with ∼4 nm, and ∼6 nm Ta 2 O 5 barrier layer, ZrO 2 -based memristive devices. Besides, multilevel resistance states have been scientifically investigated via modulating the compliance current (CC) and RESET-stop voltages, which displays that all of the resistance states were distinct and stayed stable without any considerable deprivation over 10 4 s retention time and 10 4 pulse endurance cycles. The I - V characteristics of RESET-stop voltage (from −1.7 to −2.3 V) of HRS are found to be a good linear fit with the Schottky equation. It can be seen that Schottky barrier height rises by increasing the stop-voltage during RESET-operation, resulting in enhancing the data storage memory window (on/off ratio). Moreover, RESET-voltage and CC control of HRS and LRS revealed the physical origin of the RS mechanism, which entails the formation and rupture of conducting nanofilaments. It is thoroughly investigated that proper optimization of the barrier layer at the ohmic interface and the switching layer is essential in memristive devices. These results demonstrate that the ZrO 2 -based memristive device with an optimized ∼2 nm Ta 2 O 5 barrier layer is a promising candidate for multilevel data storage memory applications.

Differential Effects of Sevoflurane Exposure on Long-Term Fear Memory in Neonatal and Adult Rats.

It remains unclear whether exposure to sevoflurane produces different effects on long-term cognitive function in developing and mature brains. In the present study, Sprague-Dawley neonatal rats at postnatal day (PND) 7 and adult rats (PND 56) were used in all experiments. We performed fear conditioning testing to examine long-term fear memory following 4-h sevoflurane exposure. We assessed hippocampal synapse ultrastructure with a transmission electron microscope. Moreover, we investigated the effect of sevoflurane exposure on the expression of postsynaptic protein 95 (PSD-95) and its binding protein kalirin-7 in the hippocampus. We observed that early exposure to sevoflurane in neonatal rats impairs hippocampus-dependent fear memory, reduces hippocampal synapse density, and dramatically decreases the expressions of PSD-95 and kalirin-7 in the hippocampus of the developing brain. However, sevoflurane exposure in adult rats has no effects on hippocampus-dependent fear memory and hippocampal synapse density, and the expressions of PSD-95 and kalirin-7 in the adult hippocampus are not significantly altered following sevoflurane treatment. Our results indicate that sevoflurane exposure produces differential effects on long-term fear memory in neonatal and adult rats and that PSD-95 signaling may be involved in the molecular mechanism for early sevoflurane exposure-caused long-term fear memory impairment.

A skyrmion content-addressable cell for skyrmion magnetic memories

Content-addressable memories (CAMs) allow searching a pattern, processing in parallel all the data stored. Beyond-CMOS technologies can provide new opportunities to improve CAM memories implementations both at the device and architectural level. In this article, we propose a ternary content-addressable memory cell based on skyrmion technology. The proposed memory cell is based on skyrmion racetrack memory. The cell is able to signal if the bit contained in the cell in form of skyrmion corresponds to an electrical input, the target of the search operation. The proposed design, verified by means of micromagnetic simulations, has an area of 0.054 μm2 and can perform a search operation in 3.3 ns with an energy of 10.5 fJ. The operation performed is non-destructive and does not require conversion between the magnetic and the electronic domains. For this reason, the designed cell has the potential to be used as a basic block for non-volatile CAM memories. Here, we propose also a layout structure to implement a CAM memory employing the proposed cell. This structure allows to achieve memory density comparable to traditional racetrack memories and execute at the same time CAM operations.

Optimizing the Performance of Wireless Sensor Network Based on Software Defined Network and Gaussian Filter

This paper presents software defining network SDN control in wireless sensor networks (WSN) to estimate packet flow, which relies on a Gaussian filter to filter the transmitted signal. The practical aim of this method is to predict the next step of packet flow earlier, which helps reduce congestion if it occurs. The proposed model (SDN-WSN with Gaussian filter) is applied to enhance signal transmission, reduce data error, reduce congestion network and reduce data overflow data. The methodology of the proposed work can be explained as follows: first: distributing nodes randomly; second: Applying the K-mean cluster to choose to select the optimum position of the head cluster node; third: connecting the network using LEACH protocol. Moreover. In this work, SDN with a Gaussian filter is proposed to control the network and minimize data error. It is possible to achieve that by adding buffer memory for each node to store data. The data transmission process is controlled by SDN, and a Gaussian filter is applied before transmitting data to minimize error data. The proposed method's simulation results proved its effectiveness in prolonging the network lifetime by nearly more than 30% rounds than out-of-date WSN, reducing the average density of memory to 20% than out-of-date WSN, and increasing the average capacitance of memory to 20% than out-of-date WSN

ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata Recovery

Emerging byte-addressable Non-Volatile Memory (NVM) technology, although promising superior memory density and ultra-low energy consumption, poses unique challenges to achieving persistent data privacy and computing security, both of which are critically important to the embedded and IoT applications. Specifically, to successfully restore NVMs to their working states after unexpected system crashes or power failure, maintaining and recovering all the necessary security-related metadata can severely increase memory traffic, degrade runtime performance, exacerbate write endurance problem, and demand costly hardware changes to off-the-shelf processors. In this article, we designed and implemented ARES, a new FPGA-assisted processor-transparent security mechanism that aims at efficiently and effectively achieving all three aspects of a security triad—confidentiality, integrity, and recoverability—in modern embedded computing. Given the growing prominence of CPU-FPGA heterogeneous computing architectures, ARES leverages FPGA’s hardware reconfigurability to offload performance-critical and security-related functions to the programmable hardware without microprocessors’ involvement. In particular, recognizing that the traditional Merkle tree caching scheme cannot fully exploit FPGA’s parallelism due to its sequential and recursive function calls, we (1) proposed a Merkle tree cache architecture that partitions a unified cache into multiple levels with parallel accesses and (2) further designed a novel Merkle tree scheme that flattened and reorganized the computation in the traditional Merkle tree verification and update processes to fully exploit the parallel cache ports and to fully pipeline time-consuming hashing operations. Beyond that, to accelerate the metadata recovery process, multiple parallel recovery units are instantiated to recover counter metadata and multiple Merkle sub-trees. Our hardware prototype of the ARES system on a Xilinx U200 platform shows that ARES achieved up to 1.4× lower latency and 2.6× higher throughput against the baseline implementation, while metadata recovery time was shortened by 1.8 times. When integrated with an embedded processor, neither hardware changes nor software changes are required. We also developed a theoretical framework to analytically model and explain experimental results.

COSMO: Computing with Stochastic Numbers in Memory

Stochastic computing (SC) reduces the complexity of computation by representing numbers with long streams of independent bits. However, increasing performance in SC comes with either an increase in area or a loss in accuracy. Processing in memory (PIM) computes data in-place while having high memory density and supporting bit-parallel operations with low energy consumption. In this article, we propose COSMO, an architecture for co mputing with s tochastic numbers in me mo ry, which enables SC in memory. The proposed architecture is general and can be used for a wide range of applications. It is a highly dense and parallel architecture that supports most SC encodings and operations in memory. It maximizes the performance and energy efficiency of SC by introducing several innovations: (i) in-memory parallel stochastic number generation, (ii) efficient implication-based logic in memory, (iii) novel memory bit line segmenting, (iv) a new memory-compatible SC addition operation, and (v) enabling flexible block allocation. To show the generality and efficiency of our stochastic architecture, we implement image processing, deep neural networks (DNNs), and hyperdimensional (HD) computing on the proposed hardware. Our evaluations show that running DNN inference on COSMO is 141× faster and 80× more energy efficient as compared to GPU.

Size-driven transition of domain switching kinetics in LiNbO3 domain-wall memory

Repetitive erasure/creation of conducting domain walls between two parallel/antiparallel domains at bipolar write voltages enables the high storage density of a ferroelectric domain-wall memory. Generally, the domain switching kinetics is described by the Kolmogorov–Avrami–Ishibashi model on the basis of domain nucleation and growth without the consideration of distributive defect pinning energies. Here, mesa-like cells were etched from single-crystal LiNbO3 thin films bonded to SiO2/Si wafers, and Pt metal contacts were deposited at their sides. The abrupt off-to-on current jump occurs at a typical domain switching time for the cell in a lateral size above 111 nm, implying the non-Kolmogorov–Avrami–Ishibashi domain switching kinetics immune to the defect pinning effect. However, the domain switching time has a broad distribution for the cell below 49 nm, implying the defect-controlled domain switching mechanism. A new model is developed to describe the size-driven transition. The reliability tests of the memory show a fast operation speed (<2 ns) and excellent reliability of on/off switching states for mass production.

Novel ESD device design for STT-MRAM memory chip

An investigation of the influence of the magnetic field induced by electrostatic discharge (ESD) current on magnetic tunnel junction (MTJ) device is presented in the paper. The transient magnetic field generated by the ESD current is not considered in the traditional CMOS ESD protection strategy, which may be a reason of the degradation of the performance and the robustness of STT-MRAM. An ESD protection circuit of STT-MRAM is proposed in the paper, including the diode-based ESD devices, the filter circuit and the power clamp. Based on the waveform analysis of the three ESD standard test models, including HBM, MM and CDM, a filter circuit is added in the ESD device to decrease the influence of the high frequency components on the magnetic device. The diode-based ESD devices are integrated in the ESD structure, which is used for the ESD window of STT-MRAM for its low operating voltage. Based on the operation mechanism of the STT-MRAM, its ESD window allows a low operating voltage, thus the diode-based devices are chosen to be integrated in the ESD device. The distribution and magnitude of the magnetic field are studied in the paper. The results show that the ESD protection circuit of STT-MRAM can effectively suppress the magnetic field generated by the ESD current, hence increasing the stability of STT-MRAM. Under the influence of the HBM, MM and CDM events, the ESD disturbance probability of the MTJ device are 2.0 × 10−12, 5.8 × 10−9 and 1.1 × 10−12 respectively. The influence of the memory density and the distance between pads and memory array are also investigated in this paper. The ESD protection strategy proposed in the paper can be adopted for the future high performance STT-MRAM.

SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection

Shrinking process technology and rising memory densities have made memories increasingly vulnerable to errors. Accordingly, DRAM vendors have introduced On-die Error Correction Code (O-ECC) to protect data against the growing number of errors. Current O-ECC provides weak Single Error Correction (SEC), but future memories will require stronger protection as error rates rise. This paper proposes a novel ECC, called Single Error Correction–Byte-Aligned Double Adjacent Error Correction (SEC-BADAEC) and its construction algorithm to improve memory reliability. SEC-BADAEC requires the same redundancy as SEC O-ECC, but it can also correct some frequent 2-bit error patterns. Our evaluation shows SEC-BADAEC can improve memory reliability by 23.5% and system-level reliability by 29.8% with negligible overheads.