Sigma-delta Research Articles

“The Throttling of the Free Press in Cuba”: Exploring Transnational Journalism and Sigma Delta Chi’s Advocacy for Press Freedom in Cuba, 1959–1962

ABSTRACT Members of Sigma Delta Chi (SDX), the largest journalism professional organization based in the United States, engaged in advocacy for transnational freedom of information and press freedom in Cuba between 1959 and 1962, between the Cuban Revolution and the Cuban Missile Crisis. Analysis of archival sources—including SDX member records, correspondence, and declassified government reports—and content in the official SDX magazine, reveals three themes: justifying a Latin America section with a primary focus on Cuba, the throttling of the free flow of information in and from Cuba, and documenting transnational flows of propaganda from Cuba and news from United States-based Cuban exiles to Cuba. Communist threats to reporters and democratic news organizations increased, and news management from the Cuban government and US government influenced information flows during this period. These findings add to the histories on free press advocacy abroad, cross-border journalism, and international press-politics in the context of US and Cuba relations.

An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

1.2 km wireless transmission of 512-QAM signals at 220 GHz using delta-sigma modulation

We have experimentally demonstrated, for the first time, photonics-aided J-band 7.48-Gb/s QPSK signals and 2.5-Gb/s 512-QAM signals using delta-sigma modulation over 1.2-km wireless link. After 1.2-km wireless transmission, the bit error rate (BER) of the 512-QAM is below the 20% soft decision forward error correction (SD-FEC) threshold of 2 × 10−2. As far as we know, this is the longest distance achieved for wireless transmission in a photonics-aided J-band wireless transmission system.

Pico-ampere resolution current measurement circuit using Gm-C filter sigma-delta modulator for low-power nanopore DNA sequencing

New generation DNA sequencers use an array of electrochemical cells equipped with nanopores, which produce pico-ampere current levels. Due to the large number of channels, low current levels and bandwidths in the order of a few kHz, in the design of these readout circuits, 2D arrays of in-channel, low noise and low power analog to digital converters are preferred. Previously many different sigma-delta modulators have been presented to convert the nanopore current signal into a digital code. Conventionally, the opamps required in these converters will eventually increase the power dissipation of each channel. In this paper a novel Gm-C filter based second order sigma-delta converter is proposed. In the given design, rather than relying on multiple opamps to achieve the necessary gain and noise performance, only a 4 transistor Gm block is used. Evaluations show that while the input referred noise remains close to previous methods, the power dissipation is considerably reduced. A prototype is also implemented to show the effectiveness of the approach. In a 180-nm design, an ENOB of 12.16 bits, RMS input referred noise of 0.2 pA at 10 kHz bandwidth and power dissipation of 8.27 μW is obtained per channel.

Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique

Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique

A Fully Synthesizable Fractional-N Digital Phase-Locked Loop with a Calibrated Dual-Referenced Interpolating Time-to-Digital Converter to Compensate for Process–Voltage–Temperature Variations

This paper presents advancements in the performance of digital phase-locked loop (DPLL)s, with a special focus on addressing the issue of required gain calibration in the time-to-digital converter (TDC) within phase-domain DPLL structures. Phase-domain DPLLs are preferred for their simplicity in implementation and for eliminating the delta–sigma modulator (DSM) noise inherent in conventional fractional-N designs. However, this advantage is countered by the critical need to calibrate the gain of the TDC. The previously proposed dual-interpolated TDC(DI-TDC) was proposed as a solution to this problem, but strong spurs were still generated due to the TDC resolution, which easily became non-uniform due to PVT variation, degrading performance. To overcome these problems, this work proposes a DPLL with a new calibration system that ensures consistent TDC resolution matching the period of the digitally controlled oscillator (DCO) and operating in both the foreground and background, thereby maintaining consistent performance despite PVT variations. This study proposes a DPLL using a calibrated dual-interpolated TDC that effectively compensates for PVT variations and improves the stability and performance of the DPLL. The PLL was fabricated in a 28-nm CMOS process with an active area of only 0.019 mm2, achieving an integrated phase noise (IPN) performance of −17.5 dBc, integrated from 10 kHz to 10 MHz at a PLL output of 570 MHz and −20.5 dBc at 1.1 GHz. This PLL operates within an output frequency range of 475 MHz to 1.1 GHz. Under typical operating conditions, it consumes only 930 µW with a 1.0 V supply.

A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs

A Partially Feedback NSSAR Embedded Third-Order Delta–Sigma Modulator With Gain-Boosted Two-Stage FIAs

A Dual-Mode Continuous–Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator

A Dual-Mode Continuous–Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator

A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation

Electric vehicle systems and smart grid systems are setting stringent development targets to respond to global trends in energy saving, carbon reduction, and sustainable environmental development. In the field of batteries, there has been extensive discussion on the estimation of battery charge. In battery management systems (BMSs) and charging/discharging systems, the accuracy of the measurement of battery physical parameters is critical, as it directly affects the system, alongside the algorithm’s estimation and error correction. Therefore, this paper proposes incorporating a low-power continuous-time delta-sigma analogue-to-digital converter into a battery measurement system to support deep learning algorithms for battery state estimation. This approach aims to maintain the accuracy of battery state estimation while reducing latency and overall system power consumption. Implemented using the UMC 0.18 μm CMOS 1P6M process, the proposed design achieves a measured signal-to-noise distortion ratio (SNDR) of 78.42 dB, an effective number of bits (ENOB) of 12.73 bits, and a power consumption of approximately 15.97 μW. The chip layout area is 0.67 mm × 0.56 mm. By applying delta-sigma modulators to energy management systems, this solution aims to increase the total number of battery monitoring units while reducing overall power consumption and construction costs.

A Σ-Δ ADC with a DPOQ system and a new multi-Stage digital filter

This paper proposes a high-precision Sigma Delta ADC for automotive electronic sensors and delves into methods for optimizing quantizers and filters, with a focus on DPOQ quantizers and hybrid CIC filters. This ADC features a Dual-path One-bit Quantization (DPOQ) System, which improves the accuracy of Sigma-Delta ADCs while reducing hardware consumption. Meanwhile, this paper presents a new multistage digital filter. The filter uses a cascade of multiple filters, including cosine-like (CL), cascaded integral comb (CIC), interpolated second-order polynomial (ISOP), and half-band (HB) filters, to enhance the ADC’s accuracy. The filter are designed using canonical signed digit (CSD) and common subexpression (CSE) optimized the design algorithm of the filter, to reduce hardware resource consumption and improve computational performance. The ADC is synthesized using 180 nm CMOS technology, achieving an output SNDR of 96.26 dB, ENOB of 15.73 bits, and total power of 518.35 uW.

4096-QAM Signal Transmission by an IM/DD System at THz Band Using Delta-Sigma Modulation

4096-QAM Signal Transmission by an IM/DD System at THz Band Using Delta-Sigma Modulation

A 0.055 mm2 Total Area Triple-Loop Wideband Fractional-N All-Digital Phase-Locked Loop Architecture for 1.9–6.1 GHz Frequency Tuning

This paper presents a wideband fractional-N all-digital phase-locked loop (WBPLL) architecture featuring a triple-loop configuration capable of tuning frequencies from 1.9 to 6.1 GHz. The first and second loops, automatic frequency control (AFC) and counter-assisted phase-locked loop (CAPLL), respectively, perform coarse locking, while the third loop employs a digital sub-sampling architecture without a frequency divider for fine locking. In this third loop, fractional-N frequency synthesis is achieved using a delta-sigma modulator (DSM) and digital-to-time converter (DTC). To minimize area, digital modules such as counters, comparators, and differentiators used in the AFC and CAPLL loops are reused. Furthermore, a moving average filter (MAF) is employed to reduce the frequency overlap ratio of the digitally controlled oscillator (DCO) between the second and third loops, ensuring stable loop switching. The total power consumption of the WBPLL varies with the frequency range, consuming between 8.8 mW at the WBPLL minimum output frequency of 1.9 GHz and 12.8 mW at the WBPLL maximum output frequency of 6.1 GHz, all at a 1.0 V supply. Implemented in a 28 nm CMOS process, the WBPLL occupies an area of 0.055 mm2.

Switching-mode audio amplifier based on a ΔΣ A/D converter

The article describes the design and implementation of a modular hardware platform intended for testing and measuring various configurations of switching-mode audio amplifiers based on sigma-delta modulation. Two single-channel power amplifier modules were designed and manufactured, along with a stereophonic module serving as the basic source of modulated signals. Additionally, measurements were conducted on the fundamental parameters of the completed amplifier, such as harmonic distortion level, dynamic range, and output power. The developed platform serves as a foundation for modifications and further advancement in the technology of building switching-mode audio amplifiers.

A second-order feedforward VCO-based ADC with continuous-time sigma-delta modulator for EEG signal recording front ends

A second-order feedforward VCO-based ADC with continuous-time sigma-delta modulator for EEG signal recording front ends

Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme

AbstractA low‐power multibit delta–sigma modulator (DSM) based on a passive and unattenuated summation scheme is proposed. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through a bidirectional sampling technique, thereby compensating for the inherent attenuation caused by passive summation, which eliminates the need for an active operational transconductance amplifier (OTA) to achieve perfect summation. Here, a second‐order DSM based on a 4‐bit first‐order passive noise‐shaping (NS) SAR quantizer is employed to satisfy the SNDR requirements exceeding 100 dB, which validates the reliability of the summation scheme. In addition, a cascoded floating inverter amplifier (FIA) is used as the core OTA to further improve system energy efficiency. Simulation results demonstrate that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and the Schreier figure‐of‐merit (FoM) of the SNDR is 183.92 dB. The results demonstrate that the proposed DSM has considerable potential for widespread application in the audio domain.

Enhancing secure transmission of ultra-high order QAM via delta-sigma modulation integrated with radial basis function neural network enhanced chaos

This paper proposes and experimentally demonstrates an ultra-high order signal security enhancement method based on delta-sigma modulation (DSM). We employ a radial basis function neural network (RBFnn) to enhance Henon chaos, effectively avoiding the degradation of chaotic dynamics, and increasing the key space from 1054 to 10385. In the experimental demonstration, we achieved high-security transmission of 16384QAM over 25 km in an intensity-modulated direct detection (IMDD) system based on DSM. The experimental results show that the ultra-high order transmission scheme based on RBFNN-chaos and DSM has superior security, with a key sensitivity of up to 10−16.

Enhancing secure transmission and key distribution for ultrahigh-order QAM via delta-sigma modulation and discrete memristive-enhanced chaos.

In this Letter, we propose a method for ultrahigh-order QAM secure transmission and key distribution based on delta-sigma modulation (DSM) and discrete memristive-enhanced chaos (DMEC). The disturbance vectors generated by the DMEC scramble the DSM signals in both frequency and time domains, resulting in highly secure DSM signals. Through the key modulation and power adjustment and then superimposing them on the encrypted signals, the method achieves simultaneous transmission of keys and signals without the need for additional spectral resources. This approach allows for secure communication with continuous key iteration and updates, offering an effective solution for implementing "one-time pad" encryption. In the experimental demonstration, we achieved a secure transmission and key distribution of a 16384QAM signal at a rate of 17.09 Gb/s over 25 km in an intensity-modulated direct detection (IMDD) system, based on DSM.

Automatic Tuning of Negative-R Circuit for High-Performance 95-dB DR 5-kHz Bandwidth Continuous-Time Delta-Sigma Modulator

Automatic Tuning of Negative-R Circuit for High-Performance 95-dB DR 5-kHz Bandwidth Continuous-Time Delta-Sigma Modulator

The Introduction of Improved Estimation Methodology via Fuzzy Sigma-Delta for Gamma-Ray Belt Conveyor

The Introduction of Improved Estimation Methodology via Fuzzy Sigma-Delta for Gamma-Ray Belt Conveyor

Design of a Sigma-Delta Analog-to-Digital Converter Cascade Decimation Filter

As the current mainstream high-precision ADC architecture, sigma-delta ADC is extensively employed in a wide range of domains and applications. This paper presents the design of a highly efficient cascaded digital decimation filter for sigma-delta ADCs, emphasizing the suppression of high folding band noise and the achievement of a flat passband. Additionally, this study addresses the critical balance between filter performance and power consumption. An inserting zero (IZ) filter is incorporated into a cascaded integrator comb (CIC) filter to enhance aliasing suppression. The IZ filter and compensation filter are optimized using the particle swarm optimization (PSO) algorithm to achieve greater noise attenuation and smaller passband ripple. The designed filter achieves a noise attenuation of 93.4 dB in the folding band and exhibits an overall passband ripple of 0.0477 dB within a bandwidth of 20 KHz. To decrease the power consumption in the filter design, polyphase decomposition has been applied. The filter structure is implemented on an FPGA, processing a 5-bit stream from a 64-times oversampling rate and third-order sigma-delta modulator. The signal-to-noise ratio (SNR) of the output signal reaches 91.7 dB. For ASIC design, the filter utilizes 180 nm CMOS technology with a power consumption of 0.217 mW and occupies a layout area of 0.72 mm2. The post-layout simulation result indicates that the SNR remains at 91.7 dB.