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Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06×/ 1.08×/ 1.36× shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03×/ 1.09×/ 1.12×/ 1.15×/ 1.17× shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33×/ 1.6×/ 2.4× higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13×/ 1.32×/ 1.37×/ 1.42×/ 1.5× higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31×/ 2.42×/ 2.55×/ 3.04× lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead.

Half-select disturb-free single-ended 9-transistor SRAM cell with bit-interleaving scheme in TMDFET technology

This paper presents a half-select disturb free single-ended 9T SRAM cell with feedback-cutting mechanism to improve the write ability and isolated read path to enhance the read stability. The proposed cell is designed based on transition-metal dichalcogenide field-effect devices (TMDFETs). HSPICE simulations are performed with 10 nm TMDFET devices at 0.7 V power supply voltage for evaluation purposes. This cell increases writing noise margin to 2.13x and 1.33x compared to DI12T and 9T cells, respectively. Given that the proposed cell is single-ended type, it therefore reduces the dynamic power consumption about 50% compared to differential cells. The results show the dynamic power reduction of 51.26%, 64.54% and 45.77% compared to DI12T, 9T and UV10T cells, respectively. Also, we achieved read delay reduction of 14.49%, 14.65% and 22.04%, compared to DI12T, 9T and UV10T cells. respectively.

A Low-Leakage Variation-Aware 10T SRAM Cell for IoT Applications

This paper presents a novel low-leakage 10T SRAM cell along with its new read circuitry. It utilizes isolated read path for the read operation that enhances the read stability of the cell as compared to conventional 6T SRAM cell. The proposed cell has been introduced for IoT applications where low power devices are the primary requirement in order to enhance the battery life. To minimize the leakage current, the PMOS transistor has been employed at the read circuitry which assists to minimize the leakage current due to induced stacking effect. The leakage current is 37.66%, 40.11% and 67.39% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. The read delay for the proposed cell is 39.80%, 89.13% and 42.33% less as compared to 6T SRAM, 8T SRAM and RDPFC 9T SRAM cells, respectively. Also, the results depict the speed improvement of 48.60%, 52.49% and 55.71% during write “0” and 46.97%, 57.5% and 54.52% improvement during write “1” operation as compared to 6T SRAM, 8T SRAM and RDFC 9T SRAM cells, respectively. The RSNM of the proposed cell is 649 mV that shows enhanced read stability over conventional 6T SRAM cell. The proposed cell proves its robustness against worst-case process variations. All the simulation work has been completed on the Cadence Virtuoso environment at 180 nm technology node.

Soft-Error Resilient Read Decoupled SRAM With Multi-Node Upset Recovery for Space Applications

Space consists of high-energy particles and high-temperature fluctuations, which causes single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is unable to tolerate this harsh environment in space. Therefore, it is necessary to design an SRAM, which can withstand this harsh environment. In order to mitigate SEUs, a radiation-hardened SRAM cell, named soft-error resilient read decoupled 12T (SRRD12T), is presented in this article. To estimate the relative performance of the proposed cell, it is compared with other contemporary designs, such as RHMN12T, RHMP12T, RHD12T, QUCCE12T, and QUATRO12T, over various important design metrics. SRRD12T can not only recover from SEU induced at any of its sensitive nodes but also from single event multi-node upsets (SEMNUs) induced at its storage node pair. Furthermore, due to the read decoupled design of SRRD12T, it exhibits the highest read stability. In addition to these, SRRD12T shows 1.14×/1.17× shorter write delay than RHD12T/RHMP12T. Moreover, SRRD12T consumes lower hold power and exhibits higher write ability than most of the comparison cells. However, these advantages are obtained by exhibiting a slightly longer read delay.

The Role of RAMP Initiative (Reading and Mathematics Project) in Raising the Level of Students in the Basic stage in Reading and Numeracy Skills

This study aimed to identify the RAMP initiative&amp;rsquo;s role (read comprehensively, answer with understanding) in raising the level of literacy skills and numeracy from the point of view of teachers. It also aimed to identify its effectiveness in improving the reading and writing level of the basic minimum stage, as an initiative that reduces the delay in reading and helps in the development of skills to help students solve mathematical problems with understanding and accommodating. Closed questionnaires were distributed to the Central Badia region; the questionnaire consisted of (35) paragraphs divided into three areas of reading, writing, and arithmetic, where 88 teachers answered the questionnaire. Statistical analysis was adopted (Statistical Package of Social Sciences (SPSS) was adopted to show the study results. The results showed a role for the RAMP initiative in raising the level of reading and numeracy skill to a reasonable degree, where the skill of reading got a good degree, was the highest skill of voice awareness to an extraordinary degree and other standards are good. Writing skill got a good degree; it was the highest, the skill of writing words and the least skill of creative writing, and also obtained the skill of calculating a good degree above (counting units) and the lowest domain (participation and composition of groups). The results showed no statistically significant differences due to variable years of experience, while the results showed statistically significant differences in favor of a bachelor&amp;rsquo;s degree.

Soft-Error-Aware Read-Decoupled SRAM With Multi-Node Recovery for Aerospace Applications

In advanced technology nodes, SRAM cells, used in the aerospace industry, have become highly susceptible to soft-error. In this brief, a Soft-Error-Aware Read-Decoupled 14T (SAR14T) SRAM cell is proposed for aerospace applications. To assess the performance of the proposed cell, it is compared with other soft-error-aware SRAM cells, like WE-QUATRO, QUCCE12T, RHD12T, RSP14T and RHBD14T. Simulation results show that all the sensitive nodes of SAR14T can reattain their initial states after being impacted by soft-error. Furthermore, the cell is capable of recovering from multi-node upset induced at its internal node-pair. Due to the employment of the read-decoupling technique, SAR14T shows the highest read stability compared to its peers. The proposed cell also proves to be the superior SRAM in terms of write ability and write delay. All these improvements are accomplished at the expense of a slightly longer read delay.

Simulation and Analysis of P-P-N 10T SRAM cell for IoT based devices

Ultra low power integrated circuits got the major attention due to its lower power dissipation in the era of Internet of Things (IoT) based smarter devices. In this context, a P-P-N based 10T SRAM cell has been designed and simulated on cadence virtuoso tool with GPDK 45nm technology node at supply voltage ranges from 0.6V to 1V. The various parameters such as static noise margin, read/write power, read/write delay of the 10T SRAM cell are determined out and compared with other considered topologies. It is interesting to notice that 10T SRAM cell shows commendable improvement in read static noise margin (RSNM) i.e. 36% and 46% as compared to conventional 6T and differential 8T SRAM cells respectively. The 10T SRAM cell also has reduction in read power of 38.52% and 38% as compared to conventional 6T and differential 8T SRAM cells respectively. The read delay of P-P-N based 10T SRAM cell is improved by 40% with compared to conventional 6T SRAM cell.

Design of an enhanced write stability, high-performance, low power 11T SRAM cell

ABSTRACT In the present era of diminishing technology nodes, stability and performance of SRAM cells deteriorate. To cope up with the above growing concerns, a new 11 T SRAM cell has been proposed which improves the stability in all operating modes of SRAM as well as the delay and power in the write mode. At worst process corner SS, the write 0 delay has been improved by 14.01%, 6.75%, 115.72% and 26.61% compared to 6 T, 8 TG, 10 TDiff and 11 T SRAM designs and write 1 delay has been improved by 9.2%, 88.639%, 13.69% and 71.42% compared to 6 T, 10 TDiff, DDS11T and 11 T designs at 0.9 V supply voltage. The impact of PVT variations has been studied on SNM, Write Margin, Read & Write delay, Leakage Power. The Monte Carlo simulation has been performed to study the effect of variability. P11T SRAM cell exhibits narrower spread in the distribution of majority design metrics. The removal of the half-select issue has been illustrated in the P11T SRAM cell using Monte Carlo simulations. Post-Layout simulation has been carried out to evaluate different design metrics at 45 nm technology node in Cadence Virtuoso.

Pengaruh Mendongeng Di Rumah Pada Kemampuan Anak Membaca Nyaring Di Depok

The purpose of this study was carried out to find out the achievements of 12 students in reading aloud before and after the experiment of fairytale method assistance conducted by parents at home and to know how much influence parent storytelling assistance has on the achievements of 12 students who experienced delays in reading aloud. Researchers used quasi-experimental one group pretest n posttes. Data collection using tests that are then processed using the statistic t-test. This research activity collaborates with their parents to be willing to do storytelling assistance activities for their children for 2 weeks. The results of data processing found a difference in the average reading ability of pre-test and post-tests in 12 children who experienced a delay in reading aloud by 5.4. T-test results obtained a significance value of 0.00 less than 0.05 then the test results were received. This research has proven the influence of storytelling treatment on the increasing ability to read aloud children, especially in children who experience delays in reading.

Effects of Articulatory Consciousness Training in First Graders with a Reading Delay: A Randomised Control Trial

ABSTRACT This paper describes a randomised control trial (RCT) of a small group intervention targeting articulatory consciousness in first graders with a reading delay (control condition: n = 57, intervention condition: n = 64). The programme in the intervention condition consisted of basic decoding and spelling tasks using articulatory cards to symbolise speech sounds. Training took place four times per week for five weeks. The control condition received “business as usual”. The results show that the children in the intervention condition learned to use the articulatory symbols, but there were no effects of the intervention on reading and phonological awareness measures. Also, there was no relationship shown between initial phonological awareness skills and gains, or lack thereof, from the intervention.

Implementation and analysis of Leakage Reduction Techniques in 6T SRAM cell

Leakage power dissipation is the dominating parameter while calculating in total power consumption of CMOS circuits specially in SRAM cells at 90 nm technology. In modern System on chips (SOCs), SRAM plays an important role because 70 to 80 percent area of any SOC is occupied by memory. So it is important to take care of leakage power dissipation and delay of memory based circuits. In this research paper, SRAM cell with hybrid Sleepy Keeper and Stack approach is proposed to optimize both the above parameters. SRAM cell using hybrid Sleepy Keeper and Stack approach leakage power consumption is 49.9 percent less and its dynamic power dissipation is 28% to 53% less as correlated to other implemented approaches. Read delay and power delay product of SRAM cell with hybrid Sleepy Keeper and Stack approach is less as compared to SRAM cell with Sleepy keeper and SRAM cell using Variable body biasing approach but these parameters value are more as correlated to conventional 6T SRAM cell and SRAM cell using stack approach.

An analytical study on effect of constitutional homeopathic medicines for single arm disability patients in age group of 6-15 years

Learning disability is a disorder of the basic physiological processes involved in using or understanding language written or spoken which manifest itself in imperfect ability to listen, speak, read, write, spell or do mathematical calculations. In this study, homeopathic medicine was prescribed to the 30 children having learning disability of age group 6 to 15. Synthesis repertory was used for repertorisation of cases and to find out constitutional medicine. Single dose of medicine was prescribed to every child at the interval of 10 to 15 days in required potency. Pre-assessment of each child was done with "Is It Dyslexia" free online evaluation by Davis Dyslexia Association. Visual Analogue Scale was used for before and after treatment analysis. Study showed significant result with mild to moderate improvement in 30 patients. Dyslexia and Dysgraphia come under category of specific developmental disorder. Dyslexia is characterized by failure to develop adequate reading skills and delay in learning to read which become apparent between the ages of 6 to 9 years. The clinical feature includes omission, distortions or substitutions of words, long hesitations, reversal of words or simply slow reading, writing difficulties are often coexisted with dyslexia. Clinical features include difficulties with spelling, syntax grammar and composition.

Highly Stable Low Power Radiation Hardened Memory-by-Design SRAM for Space Applications

In space, due to high energy particles, which cause single event upsets (SEUs), the traditional 6T SRAM cell becomes more susceptible to soft-error. In order to address this, a radiation hardened memory-by-design 10T (RHMD10T) SRAM cell is proposed in this brief. The relative strength of RHMD10T is estimated by comparing it with other contemporary cells such as QUATRO10T, QUCCE10T, QUATRO12T, QUCCE12T, NS10T and PS10T over various major design metrics. RHMD10T exhibits 1.09×/ 1.16×/ 1.26× shorter read delay than QUCCE10T/ QUATRO10T/ NS10T. RHMD10T has the highest read stability and can tolerate the highest amount of critical charge than all other comparison cells. RHMD10T consumes the lowest hold power than all other comparison cells, except NS10T. In addition, RHMD10T is the least susceptible to SEU, except QUCCE12T. All these aforementioned improvements of RHMD10T are obtained at a cost of slightly longer write delay and lower write ability.

Desempenho em tarefas de leitura e escrita de alunos surdos do 1º Ciclo do Ensino Básico ao nível do Português L2

A literatura tem constatado atrasos substanciais na capacidade de leitura e escrita em crianças surdas, sendo, contudo, escassa no que se refere à língua portuguesa. O presente estudo pretendeu caraterizar uma amostra de alunos surdos portugueses (3 meninos, 4 meninas, entre os 11 e os 12 anos de idade) do ensino fundamental em termos de grau de surdez, idade de diagnóstico, tempo de utilização de próteses/implantes e idade de ingresso numa escola especializada; e avaliar a competência destes alunos relativamente ao domínio da leitura e da escrita na sua segunda língua. Os alunos foram submetidos a uma bateria composta por 6 tarefas, que avaliaram o reconhecimento de palavras, a correspondência imagem-palavra, o cumprimento de instruções escritas, a legendagem de imagens, a compreensão de uma narrativa escrita e a produção de uma narrativa escrita. Foram observadas grandes discrepâncias em todas as variáveis independentes. Quanto às dependentes, a compreensão e a produção de uma narrativa escrita foram as competências em que os alunos revelaram maiores dificuldades. As estratégias de intervenção devem centrar-se na melhoria da compreensão da leitura, concentrando-se não apenas nas habilidades de nível básico, garantindo um conhecimento adequado do vocabulário usado em uma história específica, mas também em habilidades mais complexas, escalpelizando a sua estrutura e treinando habilidades de inferência a um nível global. Os dados revelados podem constituir um importante contributo, na medida em que a identificação de áreas fortes e fracas pode permitir um ajustamento de objetivos, métodos e/ou estratégias que, efetivamente, atendam às suas reais necessidades.

DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD

3-D NAND flash memory is gradually being widely used in solid state drives (SSDs), leading to increasing storage capacity. However, the read performance of SSD is sacrificed for decoding operations which are executed to guarantee the data reliability. No matter whether the data have bit errors, they will be sent to error correcting code (ECC) engine to decode, introducing a high read delay of SSD. Error prechecking can help to avoid the redundant decoding operations for the error-free data, but it induces extra checking overhead to the error data. Motivated by this, we carry out comprehensive experiments to analyze the distribution of bit errors in 3-D NAND flash memory. The preliminary experimental results show that there are a large number of pages read without errors in the early lifetime of 3-D NAND flash memory. Based on the observations and analyses, we propose a model to estimate the error-free ratio, and utilize it to design a dynamic error prechecking scheme (DEPS) to bypass the decoding operation for the error-free data in 3-D NAND flash memory and improve the read performance of SSD. Furthermore, by dividing a large page into small subpages, DEPS releases more error-free data, which significantly improves the read performance of SSD. Evaluation results from real-world traces demonstrate that by implementing DEPS, the average read performance of SSD is enhanced by 35%-55% with 3-D MLC NAND flash memory.

Resting EEG effective connectivity at the sources in developmental dysphonetic dyslexia. Differences with non-specific reading delay

Previous studies conducted on subjects with dysphonetic dyslexia (DD) reported inefficient timing integration of information from various brain areas. This dysregulation has been referred as neuronal dyschronia or timing deficiency. The present study examines the effective brain connectivity in Dysphonetic Dyslexic subjects (DD) compared to a group of subjects with non-specific reading delay (NSRD). The hypothesis is that the timing defect should be reflected also in the effective connectivity and the subjects with developmental dyslexia have an altered information flow different from the group of children with non-specific reading delay. The quantitative EEG at the sources of 184 children with DD was compared with that of 43 children with NRSD. The Isolated Effective Coherence (iCoh) was calculated among 17 brain regions data driven selected. To assess statistical differences in the EEG connectivity between the two groups, a Linear Mixed Effect (LME) model was applied. Two very important areas perform as hubs in the information flow: one is the left calcarine sulcus, which is more active in the DD group. The second is the left rolandic operculum, which is more active in the NSRD group. In the DD group, the calcarine sulcus is sending information to the right postcentral gyrus, the left paracentral gyrus, the right angular gyrus and the right supplementary motor area. This flow of information occurs in almost all frequency bands, including delta and theta band. Slow connections may indicate less efficient or even pathological information flow. We consider this as a neurophysiological evidence of Boder's model of dyslexia.

PMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation

In this brief, a pMOS pass gate (PPG) local bitline static random access memory (LB SRAM) architecture is proposed to reduce the read delay and resolve the half-select issue with a small area overhead. Virtual $V_{\mathrm {SS}}$ write assist is included in the architecture to improve write ability. In 22-nm fin-shaped FET (FinFET) technology, the proposed PPG LB architecture achieves an improved read delay and reduced total operation energy by 44% and 65%, respectively, at 0.4 V, compared to the full-swing LB (FSLB) SRAM architecture.

Double Node Upset Tolerant RHBD15T SRAM Cell Design for Space Applications

In this paper, a new Radiation-Hardened-By-Design (RHBD) SRAM is proposed to mitigate the Single Event Upset (SEU) and Single Event Double Node Upset (SEDU). The Monte-Carlo analysis with 5000 charge-pair samples is used to estimate the failure probability of the SRAM cells. When compared to the recently reported RHBD SRAM cells, the proposed RHBD15T SRAM achieved a zero percent failure probability for the given charge distribution. Read and write performances of the proposed SRAM cell are improved using a separate read and write circuitry at different nodes. The read delay, write delay, and power consumption are reduced by 42.3%, 5.02%, and 46.79% whereas HSNM, RSNM, and WSNM are increased by 7.18%, 78.08%, and 26.92%, respectively when compared to recently reported RSP14T SRAM cell at the cost of 2.15% increased area overhead. RHBD15T delivers $3.02\times $ times higher SEDU critical charge when compared to recently reported RSP14T SRAM cell, which states that the RHBD15T SRAM cell is more robust in a radiative environment.

Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield

This article presents a new resistive random access memory (RRAM)-based average 7T1R nonvolatile static random access memory (nvSRAM). This multiple sharing (MS) 7T1R uses MS schemes in which some of the transistors play various roles. Therefore, the MS-7T1R can perform a decoupled read, enhance write capability, and improve the restore yield with a small area cost. Furthermore, the MS-7T1R can offer two alternative modes, i.e., a high speed and a stable mode. Compared with existing technologies, such as the previous 6T-based nvSRAMs, the results show that the proposed architecture provides a remarkable restore yield and ~154% improvement in the read static noise margin (at TT corner and stable mode). In addition, the read delay improves by ~23% (at TT corner and high-speed mode). The write “1” problem of the single bitline is effectively resolved with our proposed write strategy. The static write margin of “1” is improved by ~88.6% compared with the conventional 6T ( $\beta =4$ ) at a power of 1.2 V. In addition, dynamic power is effectively reduced by the use of the single bitline and sub-word-line driver technology.

Language and Reading Progress of Young Deaf and Hard-of-Hearing Children.

We examined the language and reading progress of 336 young DHH children in kindergarten, first and second grades. Trained assessors tested children's language, reading, and spoken and fingerspelled phonological awareness in the fall and spring of the school year. Children were divided into groups based on their auditory access and classroom communication: a spoken-only group (n = 101), a sign-only group (n = 131), and a bimodal group (n = 104). Overall, children showed delays in language and reading compared to norms established for hearing children. For language, vocabulary standard scores were higher than for English syntax. Although delayed in language, children made expected gains based on hearing norms from kindergarten to second grade. Reading scores declined from kindergarten to second grade. Spoken-only and bimodal children had similar word reading and reading comprehension abilities and higher scores than sign-only children. Spoken-only children had better spoken phonological awareness and nonword reading skills than the other two groups. The sign-only and bimodal groups made similar and significant gains in ASL syntax and fingerspelling phonological awareness.