Unit Delay Research Articles

Effects of the Cascade Discharge on Hollow Plasma Properties by Using Snowplow Model Simulation

The cascade discharge of the hollow plasma device is modeled using the snowplow model. In the model, one or three condenser banks discharge between the two electrodes, with a different time delay. The results were achieved with and without the hollow plasma’s multidischarge cascade. The cascade discharge aims to increase the plasma’s energy to keep the discharge current from breaking down and to keep the plasma column compressed for an extended period. Both the cascade and the single discharges affect the pinching time. The calculated induced magnetic field increases progressively until it reaches the pinch point, and then it decreases, at which point the total discharge current reaches a low value. The magnetic field distribution was calculated as a function of the plasma radius, both with and without the cascade discharge. The model demonstrates that, both with and without a cascade discharge, the magnetic field distribution is low at the tube’s exterior wall and increases toward the axis, reaching a maximum value of 138 kG in the case of a cascade discharge and 42.5 kG with a single discharge. A delay unit resembling the one found in a hollow plasma device is utilized to manually manage the electric circuit discharge simulation.

Fiber loop quantum buffer for photonic qubits

We report a fiber loop quantum buffer based on a low-loss 2 × 2 switch and a unit delay made of a fiber delay line. We characterize the device by using a two-photon polarization entangled state in which one photon of the entangled photon pair is stored and retrieved at a repetition rate up to 78 kHz. The device, which enables integer multiples of a unit delay, can store the qubit state in a unit of fiber delay line up to 5.4 km and the number of loop round-trips up to 3. Furthermore, we configure the device with other active elements to realize integer multiplier and divider of a unit delay of a qubit. The quantum state tomography is performed on the retrieved photon and its entangled photon. We obtain a state fidelity > 94 % with a maximum storage time of 52 s with an insertion loss of 5.56 dB. To further characterize the storing and retrieving processes of the device, we perform entanglement-assisted quantum process tomography on the buffered qubit state. The process fidelity of the device is > 0.98. Our result implies that the device preserves the superposition and entanglement of a qubit state from a two-photon polarization-entangled state. This is a significant step towards facilitating applications in optical asynchronous transfer mode based quantum networks.

Ultra-Wideband Phased Antenna Array Time Delay Unit Architecture Optimization in Presence of Component Non-Idealities

Ultra-Wideband Phased Antenna Array Time Delay Unit Architecture Optimization in Presence of Component Non-Idealities

Design of a high-precision time-to-digital converter in an Elitestek Ti60 field-programmable-gate-array.

The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has garnered widespread attention due to its flexibility and high-performance capabilities. However, issues such as non-uniformity, the bubble in the tapped delay line, and the presence of certain ultra-wide delay units can significantly compromise the precision and nonlinearity of the TDC. In this paper, we propose a high-precision TDC in an Elitestek Ti60 FPGA, effectively eliminating the adverse effects of non-uniformity, the bubble, and certain ultra-wide delay units. The TDC is constructed with a 318-stage delay chain and operates at a low system clock frequency of 150MHz. The least significant bit (LSB) of the TDC is 21.92ps. The differential nonlinearity (DNL) is between (-0.976, 1.615) LSB and the integral nonlinearity (INL) is between (-1.446, 2.678) LSB. The TDC achieves a root-mean-square error of 14.783ps when utilized for measuring various time intervals.

Study of self-actuated time-controlled tower microvalves

Abstract Time-controlled microvalves are vital components of microfluidic systems, primarily used to regulate the sequential or precise introduction of reagents. However, existing time-controlled microvalves face certain limitations. For instance, those driven by magneto-thermal mechanisms require additional control elements, and fabricating some 3D time-controlled microvalves can be complex. To address these challenges, a self-driven time-controlled tower microvalve was designed and fabricated. This study investigates how structural parameters of the time-delay unit affect bubble generation and the time-delay effect. Experimental testing confirmed that the delay time of the time-controlled microvalve increases and then decreases with variations in the trapezoidal aspect ratio (a) and the upper and lower width ratios (b). Additionally, the delay time of a single unit extends as the width of the delay unit increases. The optimal parameters for the time-controlled microvalve were determined as follows: W1 =1, 000 μm, W2 =500 μm, and H=800 μm, achieving an overall delay time of 16.7±0.8 s.

Frequency-adaptive odd-harmonic repetitive control scheme for three-phase shunt active power filters

Repetitive control (RC), which can track the periodic input or suppress the periodic disturbance with a zero steady-state error, is a promising control strategy for shunt active power filters (SAPF). However, the conventional RC (CRC) scheme will suffer a severe performance degradation caused by the grid frequency variations. In this article, a frequency-adaptive odd-harmonic repetitive control scheme with a single and fixed sampling rate is proposed for SAPF to deal with grid frequency variations and provide fast transient response for RC system. The frequency-adaptability of proposed repetitive control scheme can be implemented by updating the coefficients of the approximate expression for the delay unit in repetitive controller. The FIR filter based on Lagrange linear interpolation is used to transform the multirate repetitive control system into single-rate repetitive control system to address the problems caused by the multirate repetitive control system. Moreover, a fractional-order linear compensator with a simple structure is designed to compensate the magnitude and phase of the system accurately. Compared with other classical repetitive control strategies, the proposed repetitive control scheme can provide a better adaptation to the steady-state deviation and dynamic variation of grid frequency and ensure the control performance of SAPF system. Simulation and experimental results verify the effectiveness of the proposed control scheme.

A holistic life cycle assessment of steel bridge deck pavement

Transportation serves as a cornerstone of economic development and is a significant contributor to carbon emissions. This study established a life cycle assessment model that incorporates refined carbon emission calculation parameters, streamlining the computation process while maintaining precision. A case study was conducted to quantify the life-cycle CO2 emissions of steel bridge deck pavements, a pivotal component within the transport network. The study suggests using the average annual CO2 emissions as a metric to gauge the carbon emission potential of steel bridge deck pavements with different service lives. This study addresses a void in the existing work by standardizing the grading of typical pavement diseases and quantifying the carbon emissions of the corresponding maintenance measures. It reveals that the pivotal determinant of life-cycle CO2 emissions for steel bridge deck pavements is the service performance of the paving material. Comparative analysis indicates that epoxy asphalt concrete could be deemed a low-carbon material, achieving a 77.6% reduction in life-cycle carbon emissions compared to gussasphalt concrete. Emissions during the maintenance phase constitute 66.7%–71.4% of the total life-cycle emissions, predominantly due to end-of-life and traffic delay units. The methodology and calculated data presented herein can inform subsequent carbon reduction strategies in transportation and promote the development of resilient infrastructure, thus making a substantial contribution towards carbon neutrality and climate change mitigation.

A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (VCM). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038mm2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step.

The date/delay effect in intertemporal choice: A combined fMRI and eye-tracking study.

Temporal discounting, the tendency to devalue future rewards as a function of delay until receipt, is influenced by time framing. Specifically, discount rates are shallower when the time at which the reward is received is presented as a date (date condition; e.g., June 8, 2023) rather than in delay units (delay condition; e.g., 30 days), which is commonly referred to as the date/delay effect. However, the cognitive and neural mechanisms of this effect are not well understood. Here, we examined the date/delay effect by analysing combined fMRI and eye-tracking data of N = 31 participants completing a temporal discounting task in both a delay and a date condition. The results confirmed the date/delay effect and revealed that the date condition led to higher fixation durations on time attributes and to higher activity in precuneus/PCC and angular gyrus, that is, areas previously associated with episodic thinking. Additionally, participants made more comparative eye movements in the date compared to the delay condition. A lower date/delay effect was associated with higher prefrontal activity in the date > delay contrast, suggesting that higher control or arithmetic operations may reduce the date/delay effect. Our findings are in line with hypotheses positing that the date condition is associated with differential time estimation and the use of more comparative as opposed to integrative choice strategies. Specifically, higher activity in memory-related brain areas suggests that the date condition leads to higher perceived proximity of delayed rewards, while higher frontal activity (middle/superior frontal gyrus, posterior medial frontal cortex, cingulate) in participants with a lower date/delay effect suggests that the effect is particularly pronounced in participants avoiding complex arithmetic operations in the date condition.

A 1.11 mm2 IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming at 40 MHz.

Intravascular ultrasound (IVUS) imaging catheters are significant tools for cardiovascular interventions, and their use can be expanded by realizing IVUS imaging guidewires and microcatheters. The miniaturization of these devices creates challenges in SNR due to the need for higher frequencies to provide adequate resolution. An integrated IVUS system with transmit beamforming can mitigate these limitations. This work presents the first practical highly integrated system-on-a-chip (SoC) with plane wave transmit beamforming at 40 MHz for IVUS on guidewire or microcatheters. The front-end circuitry has a 20-channel ultrasound transmitter (Tx) and receiver (Rx) array interfaced with a capacitive micromachined ultrasound transducer (CMUT) array. During each firing, all 20 Tx are excited with the same analog delay with respect to each other, which can be continuously adjusted between ~0 and 10 ns in two directions, generating a steerable plane wave in a range of ±/-50° for a phased array at 40 MHz. The unit delays are generated via a voltage-controlled delay line (VCDL), which only needs two external controls, one tuning the unit delay and the other determining the steering direction. The SoC is fabricated using a 180-nm high-voltage (HV) CMOS process and features a slender active area of 0.3 mm × 3.7 mm. The proposed SoC consumes 31.3 mW during the receiving mode. The beamformer's functionality and the SoC's overall performance were validated through acoustic characterization and imaging experiments.

A Variable Fractional Delay Filter Based True-Time-Delay Array Architecture for Wideband Beamforming

True-time delay (TTD) units are critical in Wideband Large-Scale Antenna Systems (LSASs) for resolving beam squint and frequency selective fading. In this paper, we propose a TTD array architecture for wideband beamforming that addresses the challenges posed by LSASs by utilizing variable fractional delay (VFD) filters and time delay estimations (TDEs). This study introduces a convex optimization problem to develop a novel method for designing VFD filters that can achieve high precision time delay resolution while maintaining an acceptable frequency response peak error. Using these VFD filters, we present a TDE approach with Newton-Raphson iteration update that corrects the difference in arrival time between sensors. Due to the implementation of VFD filters and fast TDE modules, the new architecture can complete beam steering and tracking in 10 ms with MATLAB simulation. Furthermore, an example was designed to demonstrate that the proposed architecture is capable of producing precise beam pointing while maintaining the bit error rate (BER) that is extremely close to the theoretical curve over the entire bandwidth.

Optimization and analysis of Spectral/Spatial optical code division multiple access passive optical network

The deployment of high-capacity transport networks while maintaining strict cost constraints is a formidable challenge for network operators in the era of networks beyond 5G (B5G) and 6G. This work explores the use of a 2D spectral-spatial optical code division multiple access (OCDMA) passive optical network (PON). It optimizes the conventional architecture to minimize the cost of deployment while maintaining desirable transmission capacity. Optimization is performed by developing a PON architecture with 2D double-weight zero cross-correlation (DW-ZCC) code that is able to support high capacity through ideal auto and cross-correlation properties. Furthermore, time delay units are employed after the spectral and spatial encoding process to minimize the use of long-span parallel optical fiber path and reduce the overall cost of deployment. Simulation analysis demonstrates that the proposed system is able to support 128 subscribers, each communicating at 10 Gbps data over a system sensitivity of approximately −21 dB. Capital expenditure (CapEx) analysis also demonstrates the effectiveness of the system optimization and reports substantial cost cuts in deploying the proposed architecture compared with the conventional counterpart.

A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.

Server Cloud Scheduling

Consider a set of jobs connected to a directed acyclic task graph with a fixed source and sink. The edges of this graph model precedence constraints and the jobs have to be scheduled with respect to those. We introduce the server cloud scheduling problem, in which the jobs have to be processed either on a single local machine or on one of infinitely many cloud machines. For each job, processing times both on the server and in the cloud are given. Furthermore, for each edge in the task graph, a communication delay is included in the input and has to be taken into account if one of the two jobs is scheduled on the server and the other in the cloud. The server processes jobs sequentially, whereas the cloud can serve as many as needed in parallel, but induces costs. We consider both makespan and cost minimization. The main results are an FPTAS for the makespan objective for graphs with a constant source and sink dividing cut and strong hardness for the case with unit processing times and delays.

An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA

The ring oscillator (RO) PUF can be implemented on different FPGA platforms with high uniqueness and reliability. To decrease the hardware cost of conventional RO PUFs, a new design using the programmable delay units is proposed, namely, PRO PUF. The programmable interconnect points (PIPs) of programmable delay units are used to enhance the configurability. The PUF cell of the proposed design has the ability to be efficiently programmed to an RO PUF at any stage by adjusting the propagation paths of the delay units. A significant number of responses can be generated by the proposed PRO PUF while consuming fewer hardware resources. To verify the performance, the proposed design has been implemented on Xilinx FPGAs and also simulated using a standard 40nm technology. The experimental results have shown that the proposed design achieves high uniqueness, reliability, and hardware efficiency. Moreover, the PRO PUF has been evaluated using a machine learning attack, the CMA-ES attack. The results have shown that the proposed structure is more resistant to common modeling attacks when compared to conventional RO-related PUF designs.

Gait Prediction and Variable Admittance Control for Lower Limb Exoskeleton With Measurement Delay and Extended-State-Observer.

The measurement delay of the feedback control system is a universal problem in industrial engineering, which will degrade output performance, especially causing undesirable chatter responses. In this study, a deep-Gaussian-process (DGP)-based method for operator's gait prediction is proposed to estimate the real-time motion intention and to compensate for the measurement delay of the inertial measurement unit (IMU). On the basis of these gait prediction uncertainties quantified by the DGP method, a variable admittance controller is designed to reduce real-time human-exoskeleton interaction torque. The reference trajectory is generated by the admittance controller, which is smoothed by the two-order Bessel interpolation. Meanwhile, the admittance parameters are self-regulated based on the defined uncertainty index of gait prediction. The extend-state observer (ESO) with backstepping iteration is adopted to compensate unmeasured system state, model uncertainties, and unmodeled dynamics of lower limb exoskeleton. The effectiveness of the proposed gait prediction and control scheme is verified by both the comparative simulations and experimental results of the human-exoskeleton cooperative motion.

To expand pharmacy-based dispensing of methadone for OUD, reduce OTP medication unit burdens and delays.

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Low-Noise Low-Power Ultrasound AFE With Continuous TGC Built in Both TIA and Beamformer.

This article presents a low-noise high-power-efficiency analog front-end (AFE) for capacitive-micromachined-ultrasonic transducers (CMUT). Implemented in 28-nm CMOS technology, the proposed AFE features three-stage continuous time-gain compensation (TGC) embedded in both trans-impedance amplifiers (TIAs) and an analog beamformer to provide a large compensation range with no extra power-consumption cost. The use of noise cancellation and capacitive feedback optimizes the noise performance of TIAs. The first stage of the TGC is built in the TIA by adjusting the positive and negative resistance loads, which are composed of voltage-controlled transistor arrays. An all-pass passive network is used as the delay unit of the analog beamformer, meanwhile achieving the second TGC stage. Phase shift for all frequency components in the ultrasound pass-band is manifested as a delay to the echoes. The third stage of the TGC is merged with a summing unit, which is a closed-loop amplifier with variable resistance feedback. The design takes into account the ability to handle large signals and power consumption, with TIA and beamforming operating at voltages of 2.5 V and 0.9 V, respectively. Experimental results show that the proposed AFE achieves a 2.11 pA/√Hz input-referred noise (IRN) at the 5 MHz center frequency of the echoes while consuming only 1.02 mW/channel. A total exponential TGC range of 60 dB with continuous ranges of 12 dB, 24 dB, and 24 dB assigned to three stages has been verified for this work.

A Novel Multilayer N-LMS Adaptive-Filter-Based Control for Synchronization and Power Quality Improvement in Grid-Tied SPV System

In the power distribution grid, a solar photovoltaic (SPV) system may experience voltage sag, swell, harmonics distortion, unbalance, and DC offset at its point of interconnection (POI). These conditions decline the power quality indices, which are escalated when the SPV system supplies power to unbalanced/ distorted loads. In this context, a multilayer normalized least mean square (N-LMS) adaptive filter-based control is proposed for the grid-tied SPV system, where the sensed grid voltages and load currents are filtered using the proposed method. Then, their dq-axis components are estimated and used to resolve synchronization issues. The estimated components are immune to negative sequence components, distortion, low-order odd harmonics (3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> , 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> , 7 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> , 9 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> ), and DC offset. The proposed control scheme has a simple structure with two tuning parameters. Moreover, it has no integrator compared with the generalized-integrator-based algorithm and only has three delay units compared with the methods based on the cascaded delay signal cancellation (CDSC). Hence, it is computationally faster than the advanced CDSC and other multilayer structure-based algorithms. Performance of the proposed method is demonstrated experimentally by implementing it on a laboratory setup of a grid-tied SPV system operating under non-ideal voltages and currents.

Real-time reconfigurable on-chip photonic frequency decoder.

A group-delay-unit-based integrated silicon photonic integrated circuit (PIC) is employed as a reconfigurable analog radio frequency decoder, which provides a real-time temporal and spectral analysis of any arbitrary multi-tone signal in the micro- and mm-wave range. The circuit is based on cascaded Mach-Zehnder interferometer embedded silicon microring resonators as variable delay units. The temporal decoding of the multi-tone input signal is demonstrated by tuning the signal with respect to the ring resonator delay and resonance. A one-to-one conformal time-to-frequency mapping provides real-time spectral decoding of the signal under test without additional digital signal processing. The idea is validated by several experimental results with single-tone and two-tone input signals in a compact, low-power, silicon PIC. The proposed real-time temporal analog frequency decoder may be very intriguing for high-speed, low-latency wireless applications, such as autonomous driving and 6G.