Tapped Delay Research Articles

Delay‐compensation block for first‐order low‐pass delta‐sigma modulators

AbstractImplementing the Delta Sigma Modulator (DSM) processing blocks on hardware is challenging due to the additional tap delays required by the digital processing blocks to process and output the result. The tap‐delays, known as latency, are necessary for the Field Programmable Gate Array (FPGA) operation to allow the logic gates to process the data at a given clock rate. These latencies alter the transfer function of the first‐order DSM as they present additional tap‐delays to the inherent delays within the DSM loop. A compensation block for the first‐order DSM is proposed to cancel‐out the effect of these latencies. By studying the transfer function, a combination of delays able to reconstruct the correct transfer function is determined. The solution was implemented on FPGA and tested using a 2.5 MHz signal. The post‐compensated DSM achieved a Signal‐to‐Noise‐and‐Distortion Ratio (SNDR) = 42 dB and an Adjacent Channel Leakage Ratio (ACLR) = 39 dB.

Extending Distributed-Based Transversal Filter Method to Spectral Amplitude Encoded CDMA

In this paper, the analog code modulation characteristics of distributed-based transversal filters (DTFs) suitable for use in spectrally encoded CDMA systems are presented. The DTF is verified as an appropriate method to use in high-speed CDMA systems as opposed to previously proposed methods, which are intended for Direct Sequence (DS) CDMA systems. The large degree of freedom of DTF design permits controlling the filter pulse response to generate well specified temporal phase-coded signals. A decoder structure that performs bipolar detection of user subbands giving rise to a Spectral-Amplitude Encoded CDMA system is considered. Practical implementations require truncating the spreading signals by a time window of duration equal to the span time of the tapped delay line. Filter functions are chosen to demodulate the matched channel and achieve improved user interference rejection avoiding the need for transversal filters featuring a large number of taps. As a proof-of-concept of the electronic SAE scheme, practical circuit designs are developed at low speeds (3-dB point at 1 GHz) demonstrating the viability of the proposal.

TUNING FOR POWER SYSTEM STABILIZER USING DISTRIBUTED TIME-DELAY NEURAL NETWORK

In this paper, a Distributed Time-Delay Neural Network (DTDNN) algorithm is used to control the Power System Stabilizer (PSS) parameters to find the reliable conditions. The proposed DTDNN algorithm apply tapped delay line memory to set the PSS. In this study, DTDNN consists of a DTDNN-identifier and a DTDNN-controller. The performance of the system with DTDNN-PSS controller is compared with a Recurrent Neural Network PSS (RNN-PSS) and Conventional PSS (C-PSS). The results show the effectiveness of DTDNN-PSS design, and superior robust performance for enhancement power system stability compared to other with different cases.

A $4\times45$ Gb/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation

This paper presents a high-swing vertical-cavity surface-emitting laser (VCSEL) driver with two-tap feed-forward equalizer (FFE) in 14-nm FinFET CMOS technology. The design features a standby mode with power-ON time below 10 ns and 86% of power saving. Based on system-level simulations, the impact of the driver swing, tap delay, and weight on the optical eye-opening is studied and it is shown that the FFE combined with high-swing driving can improve the output eye at rates beyond two times the bandwidth of the VCSEL. By applying an extra supply, the output stage is optimized to provide high swing (0.65 V) without suffering from the slow response of a transistor in the triode region. In addition, the bias and modulation currents can be adjusted to accommodate different VCSELs. The designed circuit is tested with two VCSEL types. It is bonded to common-cathode 20 and 18 GHz VCSELs, and in both the cases, data transmission at 45 Gb/s with bit error rate lower than 10−12 is measured. The total power dissipation is below 100 mW, providing a power efficiency of better than 2.11 pJ/bit. To the best of our knowledge, this design is the fastest VCSEL driver in any CMOS technology, which is also capable of burst mode operation.

A high-linearity time-to-digital converter based on dynamically delay-adjustable looped carry chains on FPGAs.

Time-to-digital converters (TDCs) act as the core component in many scientific and engineering systems which are based on high-accuracy time measurement. Traditionally, field programmable gate array (FPGA) based TDCs are constructed by organizing carry chains in the tapped delay line style, though acquiring high resolution, the differential nonlinearity (DNL) error is high in the range of 2 least significant bits (LSBs)-4 LSBs. Additionally, their long used length of the carry chain costs rather high resource, which is not friendly for multi-channel TDCs. This paper proposes a new TDC architecture based on dynamically delay-adjustable looped carry chains, which works in the Vernier mode. The TDC contains two looped carry chains, and their oscillation period difference (resolution) is dynamically adjusted by a personal computer program without manual intervene and re-compilation of the TDC circuit. A prototype TDC implemented on a Stratix III FPGA obtains the resolution of 26 ps and the DNL less than 1 LSB, but it only uses two carry chains of length of 32 each. The proposed TDC architecture opens a new way to exploit the capability of the carry chains on FPGAs for high-performance TDC applications.

Low‐complexity robust adaptive wideband beamforming based on covariance matrix reconstruction

A novel beamformer without tapped delay lines (TDLs) or sensor delay lines (SDLs) is proposed. It treats one wideband signal from a direction as multiple narrowband signals from an angular sector. To preserve the signal of interest, it reconstructs the interference-plus-noise covariance matrix using narrowband Capon spectral estimator. Eliminating the TDLs and SDLs leads to a simpler system and lower computational complexity. Moreover, it outperforms traditional wideband beamforming methods in the case of limited snapshots or high signal-to-noise ratio.

Selectable-FSR 10-GHz Granularity WDM Superchannel Filter in a Reconfigurable Photonic Integrated Circuit

We present a 10-GHz granularity reconfigurable WDM superchannel filter in a photonic integrated circuit. The filter uses a ring-resonator-assisted tapped-delay-line topology. An example configuration with two ring resonators and four tapped delay lines provides a spectral filter with a flat-top passband, a roll-off factor of 8%, a tunable central wavelength, and a selectable free spectral range, i.e., 2× or 4× the 3-dB passband bandwidth. The device was fabricated in a silicon nitride (Si3N4/SiO2) waveguide with a chip area of 0.36 cm2 and has a fiber-to-fiber insertion loss of 5 dB. We experimentally demonstrate the filter for selecting a subchannel from a WDM superchannel comprising 10-GHz subchannels with 10% and zero guard bands. Owing to the infinite impulse responses of ring resonators, this filter requires a significantly smaller area and fewer tuning elements compared with designs based on only tapped-delay-line finite-impulse-response filters. This paper contributes to the creation of chip-scale all-optical WDM superchannel transceivers and reconfigurable optical add/drop multiplexers (ROADMs).

A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA

Field Programmable Gate Arrays (FPGAs) made with 28 nm and more advanced process technology have great potentials for implementation of high precision time-to-digital convertors (TDC), because the delay cells in the tapped delay line (TDL) used for time interpolation are getting smaller and smaller. However, the bubble problems in the TDL status are becoming more complicated, which make it difficult to achieve TDCs on these chips with a high time precision. In this paper, we are proposing a novel decomposition encoding scheme, which not only can solve the bubble problem easily, but also has a high encoding efficiency. The potential of these chips to realize TDC can be fully released with the scheme. In a Xilinx Kintex-7 FPGA chip, we implemented a TDC system with 256 TDC channels, which doubles the number of TDC channels that our previous technique could achieve. Performances of all these TDC channels are evaluated. The average RMS time precision among them is 10.23 ps in the time-interval measurement range of (0–10 ns), and their measurement throughput reaches 277 M measures per second.

An 18-ps TDC using timing adjustment and bin realignment methods in a Cyclone-IV FPGA.

The method commonly used to produce a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) creates a tapped delay line (TDL) for time interpolation to yield high time precision. We conduct timing adjustment and bin realignment to implement a TDC in the Altera Cyclone-IV FPGA. The former tunes the carry look-up table (LUT) cell delay by changing the LUT's function through low-level primitives according to timing analysis results, while the latter realigns bins according to the timing result obtained by timing adjustment so as to create a uniform TDL with bins of equivalent width. The differential nonlinearity and time resolution can be improved by realigning the bins. After calibration, the TDC has a 18 ps root-mean-square timing resolution and a 45 ps least-significant bit resolution.

A hybrid elman neural network predictor for time series prediction

Artificial Neural Networks have become popular in the world of prediction and forecasting due to their nonlinear nonparametric adaptive-learning property. They become an important tool in data analysis and data mining applications. Elman neural network due to its recurrent nature and dynamic processing capabilities can perform the prediction process with a good range of accuracy. In this paper an Elman recurrent Neural Network is hybridised with a time delay called a tap delay line for time series prediction process to improve its performance. The Elman neural network with the time delay inputs is trained tested and validated using the solar sun spot time series data that contains the monthly mean sunspot numbers for a 240 year period having 2899 data values. The results confirm that the proposed Elman network hybridised with time delay inputs can predict the time series with more accurately and effectively than the existing methods.

Estimating Angle of Arrival (AOA) for Wideband Signal by Sensor Delay Line (SDL) and Tapped Delay Line (TDL) Processors

Angle of arrival (AOA) estimation for wideband signal becomes more necessary for modern communication systems like Global System for Mobile (GSM), satellite, military applications and spread spectrum (frequency hopping and direct sequence). Most of the researchers are focusing on how to cancel the effects of signal bandwidth on AOA estimation performance by using a transversal filter (tap delay line) (TDL). Most of the researchers were using two elements array antenna to study these effects. In this research, a general case of proposed (M) array elements is used. A transversal filter (TDL) in phase adaptive array antenna system is used to calculate the optimum number of taps required to compensate these effect. The proposed system uses a phase adaptive array antenna in conjunction with LMS algorithm to work an angle of arrival (AOA) estimator for wideband signals rather than interference canceller. An alternative solution to compensate for the effect of signal bandwidth is proposed by using sensor delay line (SDL) instead of fixed delay unit since it has variable time sampling in the time domain and not fixed time delay, depending on the angle of arrival of received signals. The proposed system has the ability to estimate two parameters for received signals simultaneously (the output Signal to Noise Ratio (SNR) and AOA), unlike others systems which estimate AOA only. The comparison of the simulation results with Multiple Signal Classification (MUSIC) technique showed that the proposed system gives good results for estimating AOA and the output SNR for wideband signals. (SDL) processor shows better performance result than (TDL) processor. MUSIC technique with both (SDL) and (TDL) processors shows unacceptable results for estimating (AOA) for the wideband signal. 

A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption

Presented is the first continuous-time (CT) digital infinite impulse response (IIR) filter working on signal-derived timing in lieu of a clock. We introduce a novel design method which enables the design of high-order IIR filters using only two tap delays. An event-grouping technique is also introduced to prevent parasitic oscillations in the presence of tap delay mismatches. The 1.2-V, 65-nm CMOS prototype implements a sixth-order IIR filter, with a maximum input rate of 20 Msample/s and a stop-band rejection of more than 80 dB. Without using any power-down circuitry, the chip’s power consumption tracks the input activity in a fully agile manner, and varies by more than $50\times $ , from 0.04 to 2.32 mW. The filter achieves an figure of merit (FoM) which competes with that of discrete-time (DT) filters, while avoiding the use of a clock and an antialiasing filter. Compared to prior art in CT digital signal processings, the prototype achieves 45-dB improvement in stop-band rejection and 9 $\times $ smaller delay line area. For the first time, the filtered CT digital signal is converted to synchronous mode at the end of signal chain, allowing integration with DT digital systems.

Design and Characterization of a Low-Cost FPGA-Based TDC

We present a field-programmable gate array (FPGA) implementation of a time-to-digital converter (TDC) based on a low-cost, low-area Spartan 6 device. The converter is based on a tapped delay line model. Several implementation details are discussed with a particular focus on critical blocks such as the input stage and thermometer-to-binary decoding techniques. We implemented a tap filtering technique to improve the differential nonlinearity (DNL) of the single delay line while keeping a good LSB value of 25.57 ps with a single-shot precision (SSP) between 0.69 - 1.46 LSB. Measured DNL and integral nonlinearity (INL) lie in the range between -0.90 + 1.23 and -0.43 ÷ 2.96 LSB, respectively. Measured DNL and INL lie in the range between -0.90 ÷ 1.23 and -0.43 ÷ 2.96 LSB, respectively. We then implemented an interpolating TDC to overcome the limitations of a single delay line in terms of linearity and measurement range. The interpolating TDC uses the sliding scale technique, where the time interval to be measured is asynchronous with respect to the FPGA clock, achieving DNL and INL in the range -0.072 ÷ 0.070 and -0.755 ÷ 0.872 LSB. SSP is in the 1.096 ÷ 2.815 range. Moreover, we present a novel comparison between the DNLs obtained with two different methods: statistical code density test and using a finely controlled delay source. Finally, we present the results of a Monte Carlo simulation used to investigate the effects of nonlinear propagation of the signal through the delay line.

Robust Frequency Invariant Beamforming with Low Sidelobe for Speech Enhancement

Frequency invariant beamformers (FIBs) are widely used in speech enhancement and source localization. There are two traditional optimization methods for FIB design. The first one is convex optimization, which is simple but the frequency invariant characteristic of the beam pattern is poor with respect to frequency band of five octaves. The least squares (LS) approach using spatial response variation (SRV) constraint is another optimization method. Although, it can provide good frequency invariant property, it usually couldn’t be used in speech enhancement for its lack of weight norm constraint which is related to the robustness of a beamformer. In this paper, a robust wideband beamforming method with a constant beamwidth is proposed. The frequency invariant beam pattern is achieved by resolving an optimization problem of the SRV constraint to cover speech frequency band. With the control of sidelobe level, it is available for the frequency invariant beamformer (FIB) to prevent distortion of interference from the undesirable direction. The approach is completed in time-domain by placing tapped delay lines(TDL) and finite impulse response (FIR) filter at the output of each sensor which is more convenient than the Frost processor. By invoking the weight norm constraint, the robustness of the beamformer is further improved against random errors. Experiment results show that the proposed method has a constant beamwidth and almost the same white noise gain as traditional delay-and-sum (DAS) beamformer.

A Multi-Chain Merged Tapped Delay Line for High Precision Time-to-Digital Converters in FPGAs

Field programmable gate array (FPGA)-based time-to-digital converters (TDCs) use a tapped delay line (TDL) for time interpolation to yield a sub-clock time resolution. The granularity and uniformity of delay cells in TDL determines achievable TDC time precision. To gain small delay cells in TDL, we propose a new TDL architecture by merging multiple conventional delay chains to obtain very fine intrinsic cell delays. The uniformity of these cell delays is improved by a bin decimation method so that the time interpolation with the TDL has minimum nonlinearity error. To evaluate the performance improvement using the new TDL architecture, two identical TDC channels with 1-chain, 2-chain, and 4-chain merged TDLs, respectively, were implemented in a Xilinx Kintex-7 FPGA. For time-intervals in the range from 0 to 50 ns, the average RMS precisions of these TDC pairs were measured as 8.5 ps, 5.3 ps, and 4.3 ps, respectively. The test results confirm that the proposed TDL architecture is an FPGA-independent effective method for boosting TDC precision without significant increase in hardware complexity and logic resource consumption.

Distortionless space‐time adaptive processor based on MVDR beamformer for GNSS receiver

The utilising of space-time adaptive processing (STAP) can effectively enhance the globe navigation satellite system (GNSS) receivers' performance in suppressing harsh, sustained interference. However, STAP may introduce significant biases and distortions on the cross-correlation functions, which would deteriorate acquisition and tracking performance. To achieve high-accuracy GNSS applications in challenging environments, these biases and distortions must be mitigated. A novel distortionless space-time adaptive processor based on minimum variance disstortionless response (MVDR) beamformer is proposed. By combining the information of steering vector and constraining the taps number of tapped delay line to be odd, the proposed processor can maintain the linearity of space-time filter response and it introduces no biases into the code and carrier phase measurements. The effectiveness of the proposed processor is demonstrated by theoretical analysis and simulations.

Direction-of-Arrival Estimation of Ultra-Wideband Signals in Narrowband Interference Environment Based on Power Inversion and Complex-Valued Neural Networks

We propose two-stage null-steering direction-of-arrival (DoA) estimation of ultra wideband (UWB) signals with power inversion algorithm and complex spatio-temporal neural network (CVSTNN). This method can estimate DoA more accurately than conventional methods in narrowband interference (NBI) environment. For null steering in UWB systems, it is necessary to adjust the amplitude and phase of tapped delay lines (TDLs) of CVSTNN. However, with a conventional CVSTNN, it often fails to estimate the arrival direction because of the NBI. We aim to reduce the influence of NBI in the learning process to avoid falling into a local solution by setting the initial weights of the TDLs with power inversion. In simulation results, it is shown that the two-stage method can realize higher DoA estimation accuracy than conventional methods.

A Taylor Series Approximation of Self-Interference Channel in Full-Duplex Radios

The fundamental problem in the design of a full-duplex radio is the cancellation of the self-interference (SI) signal generated by the transmitter. Current techniques for suppressing SI rely on generating a copy of the SI signal and subtracting it partly in the radio frequency (RF) and digital domains. A critical step in replicating the self-interference is the estimation of the multipath channel through which the transmitted signal propagates to the antenna. Since there is no prior model on the number of multipath reflections, current techniques assume a tap delay line filter (in the RF and digital domain) with a large number of taps, and estimate the taps in the analog and the digital domain. In this paper, using a linearization technique, we show that the self-interference channel in an indoor environment can be effectively modeled as $H(f)=C_{0} - C_{1}f$ in the frequency domain. Thus, the effective self-interference channel can be represented by two parameters $C_{0}$ and $C_{1}$ , irrespective of the multipath environment. We also provide experimental evidence to verify the above channel model and propose novel low-complexity designs for self-interference cancellation.

A Low Nonlinearity, Missing-Code Free Time-to-Digital Converter Based on 28-nm FPGAs With Embedded Bin-Width Calibrations

This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC) implemented in a 28-nm field programmable gate array (FPGA) device (Xilinx Virtex 7 XC7V690T) with novel direct bin-width calibrations. We combine the tuned tapped delay lines (TDLs) and a modified direct-histogram architecture to correct the nonuniformity originated from carry chains, and use a multiphase sampling structure to minimize the skews of clock routes. Results of code density tests show that the proposed TDC has much better linearity performances than previously published TDCs. Moreover, our TDC does not generate missing codes. For a single TDL, the differential nonlinearity (DNL) is within [−0.38, 0.87] LSB (the least significant bit: 10.5 ps) with $\sigma _{\mathrm {DNL}} = 0.20$ LSB, and the integral nonlinearity (INL) is within [−1.23, 1.02] LSB with $\sigma _{\mathrm {INL}} = 0.50$ LSB. Based on the modified direct-histogram architecture, a direct bin-width calibration method was implemented and verified in the FPGA. By implementing embedded bin-width calibrations, the histogram data of TDCs can be calibrated on the fly. After the calibration, the DNL $_{\mathrm {pk-pk}}$ (peak-to-peak DNL) and INL $_{\mathrm {pk-pk}}$ (peak-to-peak INL) can be reduced to 0.08 LSB with $\sigma _{\mathrm {DNL}} = 0.01$ and 0.13 LSB with $\sigma _{\mathrm {INL}} = 0.02$ LSB, respectively.

A hybrid time-to-digital converter based on residual time extraction and amplification

This paper presents a novel hybrid time-to-digital converter (TDC) for high resolution and wide range time measurement, where a two-stage TDC cooperates with a two-step TDC. First the input time is roughly converted by a coarse-fine two-stage TDC to guarantee wide dynamic range and small quantization error. Then the residual time from the previous conversion is obtained by an extraction circuit and further quantified by a two-step TDC for ultra fine resolution, where the extracted residue is linearly enlarged by a time amplifier (TA), followed by adopting a tapped delay line with original gate delay resolution for measurement. The TA is regulated by delay-locked-loop (DLL) to keep its gain stable under process, voltage and temperature variations. Using full-custom approach, a test chip was designed and implemented in TSMC 0.35-μm CMOS process. With an input reference clock of 100MHz, the proposed 13-bit hybrid TDC achieves a resolution of 320ps, a full range of 2.55μs and a single-shot precision of 0.73 LSB. The DNL is less than ±0.68 LSB and INL is within −1.23 LSB to 1.19 LSB.