Path Delay Research Articles

Trends in the M2 ocean tide observed by satellite altimetry in the presence of systematic errors

Trends in the deep-ocean M2 barotropic tide, deduced from nearly three decades of satellite altimetry and recently presented by Opel et al. (Commun Earth Environ 5:261, https://doi.org/10.1038/s43247-024-01432-5, 2024), are here updated with a slightly longer time series and with a focus on potential systematic errors. Tidal changes are very small, of order 0.2 mm/year or less, with a tendency for decreasing amplitudes, which is evidently a response to the ocean’s increasing stratification and an increasing energy loss to baroclinic motion. A variety of systematic errors in the satellite altimeter system potentially corrupt these small trend estimates. The Dynamic Atmosphere Correction (DAC), derived from an ocean model and used for de-aliasing, introduces a spurious trend (exceeding 0.1 mm/year in places) caused by changes in ECMWF atmospheric tides. Both operational and reanalysis atmospheric tides have spurious trends over the altimeter era. Tidally coherent errors in satellite orbits, including from use of inconsistent tidal geocenter models, are more difficult to bound, although differences between two sets of satellite ephemerides are found to reach 0.1 mm/year for M2. Orbit errors are more deleterious for some other constituents, including the annual cycle. Tidal leakage in the “mesoscale correction,” needed here to suppress non-tidal ocean variability, is a known potential problem, and if the leakage changes over time, it impacts ocean-tide trend estimation. Tests show the error is likely small in the open ocean (<0.04 mm/year) but large in some marginal seas (>0.20.2$$\\end{document}]]> mm/year). Potential contamination from other altimeter corrections (e.g., ionospheric path delay) is likely negligible for M2 but can be difficult to bound.

Optimized High Speed VLSI Implementation of the RSA Algorithm

Abstract: RSA, one of the most widely adopted public-key cryptographic algorithms, ensures secure communication by leveraging the mathematical properties of modular exponentiation and large prime factorization. However, its computational complexity and high resource demands pose significant challenges for real-time and high-speed applications. This paper addresses these challenges by proposing an optimized Very-Large-Scale Integration (VLSI) design for RSA encryption and decryption, focusing on accelerating the modular exponentiation process, which is the core of RSA computations. The design incorporates Montgomery Modular Multiplication to eliminate time-intensive division operations, enabling efficient computation in the modular arithmetic domain. It further integrates techniques such as pipelining, parallel processing, and carry-save adders to reduce critical path delays and enhance throughput. Modular exponentiation is implemented using a scalable iterative approach with the square-and-multiply method, optimized for hardware efficiency. Hardware prototypes were synthesized and tested using FPGA and ASIC platforms, demonstrating superior performance in terms of speed, area, and power consumption. The proposed architecture achieves high-speed operation while maintaining security and scalability, making it suitable for real-time cryptographic applications such as secure communication, digital signatures, and authentication systems. Comparative analysis with existing implementations highlights significant improvements, establishing the proposed design as a viable solution for next-generation secure hardware accelerators.

An Effective Single-Station Cooperative Node Localization Technique Using Multipath Spatiotemporal Information

Precise cooperative node localization is essential for the application of multifunctional integrated radio frequency (RF) sensor networks in military and civilian domains. Most geometric localization methods commonly rely on observation data from multiple receiving nodes or anchor points with known positions and synchronized clocks, producing complex system architectures and high construction costs. To address this, our paper proposes an effective single-station cooperative node localization technique, where the observation station only requires two antennas for operation. Leveraging prior knowledge of the geometry of surrounding structures, multiple virtual stations (VSs) are constructed by mining the spatiotemporal information contained in the multipath components (MPCs) to realize target positioning. The proposed method consists of two steps. In the first step, an unambiguous dual-antenna direction-finding algorithm is designed to extract the spatial information of MPCs and construct VSs, allowing a preliminary estimate of the source position (SP). In the second step, the path delays are extracted via matched filtering, while the spatiotemporal information is correlated based on the energy distribution for a more precise SP estimation. Simulations and experimental results demonstrate that our algorithm achieves high-precision single-station localization for a collaborative node, with positioning accuracy typically within 0.1 m.

Label-free imaging flow cytometry for cell classification based directly on multiple off-axis holographic projections.

Imaging flow cytometry allows highly informative multi-point cell analysis for biological assays and medical diagnosis. Rapid processing of the imaged cells during flow allows real-time classification and sorting of the cells. Off-axis holography enables imaging flow cytometry without chemical cell staining but requires digital processing to the optical path delay profile for each frame before the cells can be classified, which slows down the overall processing throughput. We present a method for real-time cell classification via label-free quantitative imaging flow cytometry using digital holography, offering a comprehensive representation of cellular structures, without the need for digital processing before automatic cell classification. We aim to develop an automatic cell classification scheme based directly on the off-axis holographic projections of the cells during flow and test it for stain-free imaging flow cytometry of white blood cells. After building a dedicated off-axis holographic microscopy system for acquiring white blood cells during flow, we apply deep-learning classification directly in the off-axis hologram space, rather than in the quantitative phase profile space. This way, we simplify computational processes and allow a significant increase in the cell classification throughput. In addition, by utilizing multiple-viewpoint holographic projections of the cells rotated during flow, instead of using a single projection, we obtain better classification results due to the additional cellular information gained. Our technique demonstrates increasing accuracy with additional viewpoint holographic projections from the optical system, achieving a 7.69% improvement when processing ten interferometric projections compared with a single interferometric projection (regular off-axis hologram). Our technique also outperforms using multiple optical path delay profile projections, requiring off-axis holographic digital preprocessing, by 17.95%, because the holographic projections are analyzed directly without preprocessing and includes the amplitude information as well. Our cell classification approach has great potential for high-throughput, high-content, label-free imaging flow cytometry for classification of large-scale cellular datasets and real-time cell classification during flow in clinical settings.

Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method

Computing the square of any large signed number using conventional methods is challenging. Therefore, parallel and partial product generation while squaring signed numbers is complex and time-consuming. This paper suggests a very large scale integration design for an efficient signed square architecture using a nonconventional method. The square of a large magnitude signed number is reduced to a lower magnitude signed multiplication and an addition operation by the Yavadunam algorithm. The suggested method finds the deficit of the signed number from the adjacent base to perform the signed square operation. The proposed design is coded using Verilog hardware description language. The synthesis and simulation of this architecture are performed using Xilinx integrated synthesis environment 14.7 software. Furthermore, this architecture is implemented on the Virtex-4, spartan-3 and spartan-6 field programmable gate array devices. The design is also coded in cadence virtuoso centos version 5. Then, it is synthesized using 180[Formula: see text]nm and 90[Formula: see text]nm technology. The validation of the proposed architecture is examined using the performance parameters, such as path delay and area. The synthesis results show improvements in delay-area complexity compared to state-of-the-art architectures. The superiority of the proposed architecture is claimed based on performance comparisons with the previous square, multipliers and signed multiplier architectures.

Research on the Modulation Characteristics of LiNbO3 Crystals Based on the Three-Dimensional Ray Tracing Method

To further study the electro-optical modulation characteristics of LiNbO3 crystals and analyze their modulation performance, a method for studying the modulation characteristics of LiNbO3 crystals, based on the three-dimensional ray tracing method, is introduced. With the help of the refractive index ellipsoidal theory, the optical properties of LiNbO3 crystals under the influence of the Pockels effect are systematically investigated. The research results show that the optical properties of LiNbO3 crystals under the action of an external electric field can be divided into two cases: the crystal optical axis is parallel to the clear light direction, and the crystal optical axis is perpendicular to the clear light direction. Subsequently, starting from Maxwell’s equation and the matter equation, the analytical expressions of optical parameters such as refractive index, wave vector, light vector, optical path, and phase delay in electro-optical crystals are derived. Finally, the propagation law of LiNbO3 crystals when the light is incident in any direction, i.e., when the optical axis of the crystal is parallel to the clear direction and perpendicular to the clear direction, and the light intensity and field of view of the LiNbO3 crystal for electro-optical modulation are discussed.

Assessing the feasibility of atmospheric water vapor monitoring with standalone BDS receiver.

The accurate monitoring of atmospheric water vapor is important for disaster prevention and environmental management. The ground-based BeiDou Navigation Satellite System (BDS) technique for atmospheric water vapor monitoring has demonstrated high accuracy and stable performance. Considering autonomy and safety, the standalone BDS receiver will be promoted in China and its surrounding areas for meteorological applications. To verify the feasibility of standalone BDS receivers for atmospheric water vapor monitoring, we evaluated the accuracy of precipitable water vapor (PWV) retrieved from standalone BDS receivers and compared it with common multi-GNSS receivers using radiosonde and ERA5 products as references. The results showed that the zenith tropospheric delay (ZTD) derived from standalone BDS receivers achieved a root mean square (RMS) of 8.2mm compared with the International GNSS Service (IGS) final zenith path delay (ZPD) products from co-located IGS Multi-GNSS Experiment (MGEX) stations. Subsequently, the PWV values derived from the two types of receivers were assessed with the radiosonde and ERA5-derived PWV. Compared with radiosonde, the RMS of the PWV differences for standalone BDS and IGS MGEX receivers was 1.9 and 1.6mm, respectively. While compared with the ERA5 products, the RMS was 1.5/1.7mm for IGS MGEX stations and 1.7/1.9mm for standalone BDS stations. The monitoring performances during rainy and non-rainy days were further analyzed, and negligible differences (less than 0.15mm) between the PWV accuracies were observed. This partially demonstrates that compared with the IGS MGEX receivers, the standalone BDS receiver is capable of monitoring atmospheric water vapor with consistent accuracy under all-weather conditions.

Circuits and mechanisms for TMS-induced corticospinal waves: Connecting sensitivity analysis to the network graph.

Transcranial magnetic stimulation (TMS) is a non-invasive, FDA-cleared treatment for neuropsychiatric disorders with broad potential for new applications, but the neural circuits that are engaged during TMS are still poorly understood. Recordings of neural activity from the corticospinal tract provide a direct readout of the response of motor cortex to TMS, and therefore a new opportunity to model neural circuit dynamics. The study goal was to use epidural recordings from the cervical spine of human subjects to develop a computational model of a motor cortical macrocolumn through which the mechanisms underlying the response to TMS, including direct and indirect waves, could be investigated. An in-depth sensitivity analysis was conducted to identify important pathways, and machine learning was used to identify common circuit features among these pathways. Sensitivity analysis identified neuron types that preferentially contributed to single corticospinal waves. Single wave preference could be predicted using the average connection probability of all possible paths between the activated neuron type and L5 pyramidal tract neurons (PTNs). For these activations, the total conduction delay of the shortest path to L5 PTNs determined the latency of the corticospinal wave. Finally, there were multiple neuron type activations that could preferentially modulate a particular corticospinal wave. The results support the hypothesis that different pathways of circuit activation contribute to different corticospinal waves with participation of both excitatory and inhibitory neurons. Moreover, activation of both afferents to the motor cortex as well as specific neuron types within the motor cortex initiated different I-waves, and the results were interpreted to propose the cortical origins of afferents that may give rise to certain I-waves. The methodology provides a workflow for performing computationally tractable sensitivity analyses on complex models and relating the results to the network structure to both identify and understand mechanisms underlying the response to acute stimulation.

Designing RNS-based FIR filter with Optimal area, Delay, and Power via the use of Swift Adders and Swift Multipliers

Based on the Residue Number System (RNS), Finite Impulse Response filters have gained prominence in digital signal processing due to their efficiency in handling complex computations. This work presents a comprehensive analysis on optimizing area, delay, and power in the FIR filter by exploring different adders and multipliers. Three prominent adders, namely Ripple Carry Adder, Kogge Stone Adder, and Proposed Adder, are evaluated for their impact on area and delay. The choice of adder influences the overall performance of the FIR filter, and a careful selection is made based on the trade-offs between area and delay. Furthermore, various multipliers, including Booth, Baugh-Wooley, Braun, and Array, are compared in terms of their efficiency in power consumption. Multipliers contribute significantly to the overall power consumption, and the analysis involves selecting the most suitable multiplier for achieving the desired power optimization. The various arrangements of swift adders and swift multipliers were suggested and executed in the Finite Impulse Response (FIR) filter and then the RNS algorithm was applied to it. The comparison of 8-tap 8-bit of the proposed adder with the array multiplier shows that the area is reduced by 52.70% with other combinations and by comparing the RCA adder with the array multiplier, the critical path delay is reduced by 38.51% and the maximum frequency is produced by the KSA adder with Braun multiplier which is increased by 29.78% with other combinations.

Isolated microgrid frequency stabilization through nonlinear model predictive control of a gas engine generator set

Gas engine generator sets are applied in microgrids due to their capability to provide reliable, responsive and efficient distributed power generation, enhancing grid resilience and enabling the integration of renewable energy sources. This article proposes a methodology for stabilizing the frequency of an isolated microgrid subjected to a measurable disturbance by controlling the power of a premixed turbocharged natural gas engine. Control difficulties of this task include strongly nonlinear dynamics, time delay in the air-fuel path and constrained operating conditions. Conventional control methods like proportional-integral control have difficulties solving these problems, and require extensive tuning efforts and gain scheduling to deliver acceptable performance, prompting adoption of advanced control strategies. The presented approach utilizes a cascaded control architecture with a nonlinear model predictive controller (NMPC) for high level control and engine specific low-level controllers for controlling the intake manifold pressure and air-fuel ratio. The NMPC captures the inherent nonlinear dynamics, accounts for an input delay and handles state-dependent constraints. The cascaded control architecture enables the usage of a comparably simple model for the NMPC design, reducing the computational cost and the parametrization effort. This additionally enables application of the high level controller for different gas engine types and allows design of the controller in a simple simulation environment prior to the experiments on the real engine. Experimental results highlight the NMPC’s ability to control the engine at its physical limits over the entire load range without inducing frequency oscillations using just one parameter set. This emphasizes the robustness of the presented approach, making it a promising solution for real-world applications.

An Efficient Multi-Level 2D DWT Architecture for Parallel Tile Block Processing with Integrated Quantization Modules

A multi-level 2D Discrete wavelet transform (DWT) architecture for JPEG2000 is proposed, enhancing speed through parallel processing multiple tile blocks. Based on the lifting scheme, folded architecture and unfolded architecture achieving critical path delay with only one multiplier are designed to increase throughput rate. Connecting the folded and unfolded architecture through a pipeline architecture ensures uniform throughput rates across all DWT levels within a singular clock domain. Computational resource consumption is reduced by adjusting the timing to allow one folded architecture to process three tile blocks of three to five levels of DWT, and a transposing module requiring merely six registers is devised to decrease storage resource consumption. The quantization module, crucial for code-word control in JPEG2000, is integrated into the scaling module with minimal additional resource expenditure. Compared to the existing architecture, the analysis demonstrates that the proposed architecture exhibits enhanced hardware efficiency, with a reduction in transistor-delay-product (TDP) of no less than 14.69%. Synthesis results further reveal an area reduction of at least 26.64%, and a decrease in area-delay-product (ADP) by a minimum of 29.89%. Results from FPGA implementation indicate a significant decrease in resource utilization.

Overload cascading failure detection algorithm for multi-layer supply chain network considering delay probability factor

At present, the supply chain is multi-layered and complicated, and its failure detection is based solely on the characteristic threshold, which does not lack the ability to describe the complex supply chain. An overload cascading failure detection algorithm for multi-layer supply chain network considering delay probability is proposed. Based on the multi-layer supply chain network including raw material suppliers, manufacturers, distributors and retailers, the overload cascading failure model of the multi-layer supply chain network is constructed through networking, and the overload cascading failure process of the multi-layer supply chain network is described through three aspects: initial load, node capacity and overload node load distribution. By monitoring and analyzing the status update messages of each node in the supply chain network, and considering the delay probability factor, the node and path that may lead to cascading failure are identified by predicting the delay probability of the next message through the historical message delay probability, and the overload cascading failure detection of the multi-layer supply chain network is realized. The experimental results show that the algorithm can effectively detect the failure of each overloaded enterprise node in the multi-layer supply chain network, which is helpful to enhance the early warning and response ability of the cascade failure of the supply chain network. The algorithm can realize the failure detection of supply chain network under different attack conditions and initial failure ratio of nodes, and measure the anti-risk ability of supply chain network. Under deliberate attack and when the initial attack node is a supplier network layer node, it has a greater impact on the multi-layer supply chain network.

Functionally Possible Path Delay Faults With High Functional Switching Activity

Functionally Possible Path Delay Faults With High Functional Switching Activity

Adaptive generation of optical single-sideband signal with dually modulated EML.

The optical single sideband (SSB) transmitter based on dual modulation of an electro-absorption modulation laser (D-EML) has attracted considerable attention for its capability of monolithic integration and high output power. A model-based modulation method has been developed recently for generating high-quality optical SSB signals with this D-EML scheme. However, this method requires accurate characterization of the EML's chirps and pre-compensation for frequency responses of all-optical/electrical components, as well as the path difference between two driving signals. This imposes notable requirements on the transmitter characterization in practical applications. In this paper, we propose an adaptive method to approach the required responses of the pre-compensation filters for this optical SSB transmitter. This method avoids cumbersome device characterization and shows great resilience to the variation of system parameters. By using the proposed adaptive method, we generate a 56 Gb/s optical SSB orthogonal frequency-division multiplexed signal with the sideband suppression power ratio exceeding 21 dB. It is convenient with this method to switch the devices, i.e., directly modulated laser (DML) or electro-absorption modulator (EAM), to be pre-compensated for the optical SSB signal generation. Moreover, this method exhibits good tolerance to the path delay (±15 ps) between DML and EAM, as well as modulation depth. We also successfully transmit this signal over 80 km long standard single-mode fiber.

Towards fine-grained load balancing with dynamical flowlet timeout in datacenter networks

In modern datacenter networks (DCNs), load balancing mechanisms are widely deployed to enhance link utilization and alleviate congestion. Recently, a large number of load balancing algorithms have been proposed to spread traffic among the multiple parallel paths. The existing solutions make rerouting decisions for all flows once they experience congestion on a path. They are unable to distinguish between the flows that really need to be rerouted and the flows that potentially have negative effects due to rerouting, resulting in frequently ineffective rerouting. Fine-grained rerouting will also cause severe packet reordering, especially in asymmetric topology scenarios. To address the above issues, we present a fine-grained traffic-differentiated load balancing (TDLB) mechanism, which aims to distinguish flows that are necessarily to be rerouted and reroute traffic in fine-grained without packet reodering. Specifically, TDLB distinguishes the traffic that must be rerouted through the host pair information in the packet header, and selects an optimal path for rerouting. To prevent severe packet reodering caused by excessive path delay differences, TDLB dynamically adjusts the flowlet timeout to segment the traffic and select the optimal path for rerouting. The NS-2 simulation results show that TDLB effectively reduces tail latency and average flow completion time (FCT) for short flows by up to 49% and 46%, respectively, compared to the state-of-the-art load balancing schemes.

A lightweight dual-link accelerated authentication protocol based on NLFSR-XOR APUF

Physical Unclonable Function (PUF) circuits, as a lightweight hardware security primitive, can provide reliable authentication for resource-constrained Internet of Things (IoT) devices. However, in real-time environments and systems, authentication of embedded devices has strict requirements on resources and low latency. Therefore, this paper proposes a lightweight dual-link accelerated authentication protocol design based on NLFSR-XOR APUF, through the study of Non-Linear Feedback Shift Registers (NLFSR) and XOR APUF circuits. First, the scheme utilizes the symmetric path delay deviation characteristics of APUF and the complexity of NLFSR state transitions to form a nonlinear output function that changes with the challenge signal. Then, a lightweight and attack-resistant authentication protocol is established by combining the random probability of shuffling array bits with the XOR confusion mechanism. Finally, the advantages of GPU parallel computing and AES T-table reconfiguration scheme are used to achieve an accelerated and side-channel attack-resistant authentication protocol. Experimental results show that the PUF circuit can effectively resist various modeling attacks, including logistic regression (LR), artificial neural network (ANN), and support vector machine (SVM). The security of the protocol has been formally verified, and the prototype has been implemented on the Xilinx xc100T development board, effectively resisting deception attacks, physical attacks, and modeling attacks. The protocol's area overhead in terms of LUT and encryption time is reduced by 58.6 % and 67.8 %, respectively, compared to similar protocols.

Dynamic spatial price equilibrium, dynamic user equilibrium, and freight transportation in continuous time: A differential variational inequality perspective

In this paper we provide a statement of dynamic spatial price equilibrium (DSPE) in continuous time as a basis for modeling freight flows in a network economy. The model presented describes a spatial price equilibrium due to its reliance on the notion that freight movements occur in response to differences between the local and distant prices of goods for which there is excess demand; moreover, local and distant delivered prices are equated at equilibrium. We propose and analyze a differential variational inequality (DVI) associated with dynamic spatial price equilibrium to study the Nash-like aggregate game at the heart of DSPE using the calculus of variations and optimal control theory. Our formulation explicitly considers inventory and the time lag between shipping and demand fulfillment. We stress that such a time lag cannot be readily accommodated in a discrete-time formulation. We provide an in-depth analysis of the DVI's necessary conditions that reveals the dynamic user equilibrium nature of freight flows obtained from the DVI, alongside the role played by freight transport in maintaining equilibrium commodity prices and the delivered-price-equals-local-price property of spatial price equilibrium. By intent, our contribution is wholly theoretical in nature, focusing on a mathematical statement of the defining equations and inequalities for dynamic spatial price equilibrium (DSPE), while also showing there is an associated differential variational inequality (DVI), any solution of which is a DSPE. The model of spatial price equilibrium we present integrates the theory of spatial price equilibrium in a dynamic setting with the path delay operator notion used in the theory of dynamic user equilibrium. It should be noted that the path delay operator used herein is based on LWR theory and fully vetted in the published dynamic user equilibrium literature. This integration is new and constitutes a significant addition to the spatial price equilibrium and freight network equilibrium modeling literatures. Among other things, it points the way for researchers interested in dynamic traffic assignment to become involved in dynamic freight modeling using the technical knowledge they already possess. In particular, it suggests that algorithms developed for dynamic user equilibrium may be adapted to the study of urban freight modelled as a dynamic spatial price equilibrium. As such, our work provides direction for future DSPE algorithmic research and application. However, no computational experiments are reported herein; instead, the computing of dynamic spatial price equilibria is the subject of a separate manuscript.

Clock synchronization characterization of the Washington DC metropolitan quantum network (DC-QNet)

Quantum networking protocols relying on interference and precise time-of-flight measurements require high-precision clock synchronization. This study describes the design, implementation, and characterization of two optical time transfer methods in a metropolitan-scale quantum networking research testbed. With active electronic stabilization, sub-picosecond time deviation (TDEV) was achieved at integration times between 1 and 105 s over 53 km of deployed fiber. Over the same integration periods, 10-ps level TDEV was observed using the White Rabbit–Precision Time Protocol over 128 km. Measurement methods are described to understand the sources of environmental fluctuations on clock synchronization toward the development of in situ compensation methods. Path delay gradients, chromatic dispersion, polarization drift, and optical power variations all contributed to clock synchronization errors. The results from this study will inform future work in the development of compensation methods essential for enabling experimental research in developing practical quantum networking protocols.

Anti-machine-learning-attack strong PUF design based on multi-path delay selection strategy

Physical unclonable functions (PUF) have significant potential for application in information security. However, strong PUFs are vulnerable to machine learning (ML) modeling attacks, which severely limit their application in device authentication. Despite a variety of resistance techniques, strong PUFs suffer from hardware cost and stability deficiencies. This study proposes an anti-machine-learning-attack strong PUF based on a multi-path delay selection strategy through research on the entropy source of a strong PUF and the delay signal selection mechanism. First, we constructed a deviation source circuit based on multiplexers to increase the diversity of the delay signal transmission paths. Second, we constructed a delay selection circuit based on the logic gates. This circuit dynamically selects the delay signals with the same transmission path in the deviation source using AND and OR gates. Subsequently, the deviation source and delay selection circuits were utilized to construct the delay module, and the interconnection module was inserted between the delay modules to achieve alternating appearances of different types of logic gates along the delay path. Finally, RS flip-flops were employed to make decisions on the bias signals with the same delay path, and the final response was output through an XOR operation. The proposed PUF was implemented on a Xilinx Artix-7 FPGA, and the prediction accuracy of the four typical ML models was below 59 % (with 500,000 challenge-response pairs as the training set). Moreover, the proposed PUF structure is scalable and exhibits better performance in terms of hardware cost and stability than existing classic structures.

HEAD: High-Speed Approximate HEterogeneous ADder for Error-Resilient Applications

Media processing applications can tolerate error up to a certain limit due to the perceptual limitations of the human eye. Since adders are ubiquitous in power-hungry media processing applications, they can be approximated without much compromise in quality. An adder with better error characteristics without significant compromise in area and power is required to meet the future demands of ever-increasing computational needs. In order to achieve the same, a novel segmentation technique has been proposed. By varying the number of bits in each segment, three different designs are proposed, each with its advantage. Each proposed adder is segmented into three portions, namely Most Significant Portion (MSP), Intermediate Significant Portion (ISP) and Least Significant Portion (LSP). The sub-adder’s sum in each portion is computed concurrently to reduce the critical path delay. The proposed heterogeneous adder (HEAD) designs achieve better accuracy than the state-of-the-art designs. Synthesis results show that HEAD consumes less area up to 41.8% and consumes less power ranging from 0.8% to 51%, than existing adders. Exhaustive simulations are carried out on benchmarking image sharpening application to prove that the proposed adders obtain a better quality-effort tradeoff than the existing designs.