Delay-line Circuit Research Articles

A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction

This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μm digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication.

A ±0.5-mV-Minimum-Input DC-DC Converter With Stepwise Adiabatic Gate-Drive and Efficient Timing Control for Thermoelectric Energy Harvesting

This paper presents a step-up DC-DC converter that uses a stepwise gate-drive technique to reduce the power FET gate-drive energy by 82%, allowing positive efficiency down to an input voltage of ±0.5 mV—the lowest input voltage ever achieved for a DC-DC converter as far as we know. Below ±0.5 mV the converter automatically hibernates, reducing quiescent power consumption to just 255 pW. The converter has an efficiency of 63% at ±1 mV and 84% at ±6 mV. The input impedance is programmable from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\Omega $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$600~\Omega $ </tex-math></inline-formula> to achieve maximum power extraction. A novel delay line circuit controls the stepwise gate-drive timing, programmable input impedance, and hibernation behavior. Bipolar input voltage is supported by using a flyback converter topology with two secondary windings. A generated power good signal enables the load when the output voltage has charged above 2.7 V and disables when the output voltage has discharged below 2.5 V. The DC-DC converter was used in a thermoelectric energy harvesting system that effectively harvests energy from small indoor temperature fluctuations of less than 1°C. Also, an analytical model with unprecedented accuracy of the stepwise gate-drive energy is presented.

AlScN-Based SAW Magnetic Field Sensor for Isolated Closed-Loop Hysteretic Current Control of Switched-Mode Power Converters

This letter uses a surface acoustic wave magnetic field sensor for measurement and closed-loop current control of the inductor current in a GaN-based dc-dc power converter. The sensor is based on aluminium scandium nitride thin films with relatively high Sc concentration of 32% and fabricated on low-cost 8-in silicon substrate, with a magnetostrictive FeCoSiB film on top of a SAW delay line. The device has dc and bidirectional current measurement capability (derived from the magnetic flux density around a current trace) and is operated electrically isolated above the current trace. With permanent magnets as magnetic bias, the setup has a usable bidirectional current range of ±5 A. A phase detector IC measures the phase shift between the 296 MHz, 19 dBm input, and 35 dB attenuated output signal of the delay line sensor. The active sensor area has a distance of 2.5 mm from the current trace. In a 1.2 mT bias, the sensor is operated with a sensitivity of 18.28°/mT and bipolar current range of up to ±5 A. The sensor signal is enhanced by an analog filter to compensate the over 1 µs delay from the delay line and readout circuit. Finally, the sensor is used as the input of an analog hysteretic current control loop. The closed-loop current control operation is demonstrated using a 48 V GaN-based half-bridge dc-dc converter with 16 kHz triangular inductor current.

A High-Performance UWB Gaussian Pulse Generator: Analysis and Design

This article aims to investigate the limitations on the amplitude of the conventional step recovery diode (SRD)-based Gaussian pulse transmitter and techniques to overcome the limits. The operation of the modified design is examined and compared with a conventional configuration. The results show a considerable increase in the pulse amplitude. The high pulse amplitude of the modified configuration represents an increase in the transmitter’s output power and its improved probing range. The Gaussian pulse is converted into the first derivative Gaussian pulse using a 90° broadband coupler as a differentiator and a semi-differentiator delay line circuit with balanced stubs. The output monopulse generated using the balanced stub delay line has more symmetric sidelobes with narrower pulsewidth than the 90° couplers. Experimental results have shown the high performance of the proposed transmitter over the conventional designs in terms of pulse amplitude and symmetry.

Differential signal balancer embedded in silicon LSI as smallest common-mode filter combined bifilar coupling inductors and stacked delay lines

The new differential signal balancer embedded in the metal wiring layer of silicon LSI having increased wiring density and improved characteristics is developed. An internal delay line circuit is stacked vertically to obtain a larger delay time than the extended horizontally structure, and the two inductors for common-mode noise rejection are configured with a stacked bifilar winding structure to obtain higher effective coupling and lower parasitic resistance. Compared to the previous design, the common-mode rejection ratios at 2.4 GHz and 5.4 GHz have been improved by 4.0 dB and 4.6 dB in a smaller area of 120 × 230 μm2, respectively.

Solid-State Pulse-Forming Modules by Utilizing the 2-D Electrode Manufacturing Technology

Nowadays, most of solid-state circuits are fabricated through the application of the 2-D electrode manufacturing technology (printed circuit). In this paper, solid-state pulse-forming modules using 2-D electrode manufacturing technology are presented to produce long pulse duration while less space volume is being occupied. First, on a glass-ceramic (dielectric constant 225) substrate with the dimension of 250 mm × 95 mm × 4 mm, as meander line is the usual delay-line circuit in printed circuit boards, the meander pulse-forming line is used to deliver a highvoltage pulse with pulse duration longer than 120 ns by simulation and test validation. Furthermore, we also discuss the double parallel meander-line and the “V” shaped meander-line in this section. Second, with the same substrate, the LC pulse-forming module is used to generate the high-power pulse with good square pulse quality. By changing the inductance L, this module can be adjusted to deliver pulses with different durations. Third, planar concentric ring PFL is proposed with simulation analysis. In simulation, the planar concentric ring PFL is designed using an attractive storage medium-Barium Titanate (BaTiO 3 ) baseceramics (dielectric constant~1000). At last, a compact PFL based on the structure of multilayer ceramic capacitor is introduced, and can generate a quasi-square pulse in simulation. These various types of solid-state pulse-forming modules may be the potential component in the compact pulsed power systems to generate high-voltage, long-duration pulses.

Ultra‐low power pass‐transistor‐logic‐based delay line design for sub‐threshold applications

Designs that operate at sub-threshold voltages are a promising response to the ultra-low power demands of many modern applications with relaxed performance requirements. Towards this approach, a pass-transistor-logic-based programmable delay line (DL) circuit is presented that is designed specifically for sub-threshold operation. Compared with the commonly used design, the DL consumes 79.2% less dynamic energy, 83.5% less leakage power, 47.2% better linearity across codewords, 58.6% smaller active area, and with similar resiliency to variations across Monte Carlo simulations.

In brief

PAGE 1910 A paper presented by researchers from the University of Southern California, USA, and the Birla Institute of Technology and Science, India, shows a new pass-transistor-logic based programmable delay line circuit. Compared to the commonly used design, it consumes 79.2% less dynamic energy, 83.5% less leakage power, has 47.2% better linearity across codewords and 58.6% smaller active area, with similar resiliency to variations across Monte Carlo simulations. PAGE 1906 Researchers at Zurich Research Laboratory in Switzerland present a novel architecture for Taomlinson-Harashima precoders. In this design the modulo operation is taken out of the loop so that the remaining infinite impulse response filtering is performed entirely in carry-save adder arithmetic to reduce the feedback delay, as no conversion to binary format is required within the loop. This programmable delay line circuit has a more compact active area and uses less power than conventional designs. PAGE 1954 A non-stoichiometric GaAs layer is investigated with terahertz emission spectroscopy by a group of researchers at the Center for Physical Sciences and Technology and Teravil Ltd, in Lithuania. The results obtained revealed the existence of parallel to the surface THz radiating electric dipoles. They also showed that non-stoichiometric GaAs enhances THz radiation in comparison with one of the best THz surface emitters: p-InAs and semiconductor nanowires. There are proposals to use this technology in asymmetric and memory links. PAGE 1929 A 3D-printed, ceramic resin spherical resonator X-band dual-mode bandpass filter has been created by researchers in China and the UK. They believe this to be a first of its kind, with the stereolithography-produced ceramic resin structure providing excellent thermal stability, heat handling and mechanical strength with low weight. Non-stoichiometric GaAs has potential for bias-free THz surface emitters. PAGE 1912 Researchers from Konkuk University and Hanbat National University in Korea present a novel image descriptor for fingerprint liveness detection. They propose to accumulate multiple smoothing results by globally fast edge-aware filtering. Experimental results support the efficiency and robustness of the method compared with previous local image descriptors. The 3D-printable ceramic resin can handle heat much better than other resins but is still much lighter than metal alternatives. The proposed method can be directly applied to mobile devices to improve security for users.

Sequential Filtering Processes Shape Feature Detection in Crickets: A Framework for Song Pattern Recognition.

Intraspecific acoustic communication requires filtering processes and feature detectors in the auditory pathway of the receiver for the recognition of species-specific signals. Insects like acoustically communicating crickets allow describing and analysing the mechanisms underlying auditory processing at the behavioral and neural level. Female crickets approach male calling song, their phonotactic behavior is tuned to the characteristic features of the song, such as the carrier frequency and the temporal pattern of sound pulses. Data from behavioral experiments and from neural recordings at different stages of processing in the auditory pathway lead to a concept of serially arranged filtering mechanisms. These encompass a filter for the carrier frequency at the level of the hearing organ, and the pulse duration through phasic onset responses of afferents and reciprocal inhibition of thoracic interneurons. Further, processing by a delay line and coincidence detector circuit in the brain leads to feature detecting neurons that specifically respond to the species-specific pulse rate, and match the characteristics of the phonotactic response. This same circuit may also control the response to the species-specific chirp pattern. Based on these serial filters and the feature detecting mechanism, female phonotactic behavior is shaped and tuned to the characteristic properties of male calling song.

A high-precision synchronization circuit for clock distribution

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm2, and the power consumption is 1.64 mW at 500 MHz.

An X-ray imaging device based on a GEM detector with delay-line readout

An X-ray imaging device based on a triple-GEM (Gas Electron Multiplier) detector, a fast delay-line circuit with 700 MHz cut-off frequency and two dimensional readout strips with 150 μm width on the top and 250 μm width on the bottom, is designed and tested. The localization information is derived from the propagation time of the induced signals on the readout strips. This device has a good spatial resolution of 150 μm and works stably at an intensity of 105 Hz/mm2 with 8 keV X-rays.

Synthesis algorithm of a multi-channel lattice-form optical delay-line circuit

A novel synthesis algorithm for multi-channel ( M⩾2) lattice form optical delay-line circuit is presented in this paper. This circuit offers multi-port FIR optical filter with delay time of N Δ τ (Δ τ: unit delay time). Synthesis algorithm is based on division of total transfer matrix into unit blocks. Developed method confirms that 1× M optical delay-line circuit offers same transmission characteristics as 1× M FIR digital filter. Band-pass flat group delay type filter is considered as an example in this paper. It is also confirmed that proposed delay-line circuit can realize 100% power transmittance.

Study of delay-line readout for GEM detector

The delay-line readout method is suitable for the position sensitive detectors in the early stage of high energy physics experiment at low-rate environment. In this paper, we present a fast delay-line circuit (cut off frequency: 0.7 GHz) equipped with a triple-GEM (Gas Electron Multiplier) detector for X-ray imaging. Using 8 keV X-rays and readout strips with 0.15 mm width and 0.4 mm pitch, the experiment result shows that the position resolution of the detecting system is less than 100 μ m at a counting rate of 10 5 Hz . A full simulation model has been developed for the design of delay-line electric circuit.

High-Resolution Delay Testing of Interconnect Paths in Field-Programmable Gate Arrays

We present a new method of performing high-resolution path delay testing on designs targeted to field-programmable gate arrays. Our built-in self-test (BIST) architecture uses an on-chip delay line element to set the launch time of each test pattern generator to its optimum point for stressing paths in the routed chip. The rising and falling edges of each test pattern are controllable with high precision, and consequently, our test architecture catches very small timing faults that exist in the path. For example, on Xilinx Virtex-4, we catch defects as small as 78 ps using the IDELAY delay line circuit that is available on that device. Our approach was validated on Virtex-4, and the same method can be applied to any device that supports on-chip delay lines that are adjustable at runtime. Furthermore, our architecture simultaneously tests multiple paths to reduce the overall test time.

Synthesis of a multichannel lattice-form optical delay-line circuit with ring waveguides

This paper presents a one-input M -output (1 x M) circuit configuration and a synthesis algorithm for realizing an optical infinite impulse response (IIR) lattice filter having M -output channels (M > or =2) .The circuit configuration has a multilayer structure consisting of multiple Mach-Zehnder interferometers with delay time difference of Deltatau. It is a natural extension of the conventional two-port optical IIR lattice circuit (M =2) . Synthesis algorithm is derived to obtain all unknown circuit parameters. The proposed synthesis algorithm is based on factorizations of the paraunitary total transfer matrix. Simulation result demonstrates the effectiveness of the proposed multichannel IIR design scheme. The synthesis algorithm for M - channel IIR filter is considered lossless in this paper, which implies that the filter must be power complementary.

New topology for a variable differential delay line using the FGMOS transistor

In this study, we show that floating gate MOS (metal oxide semiconductor) transistors support a low-voltage and low-power variable analogue differential delay line circuit for signals in the audio frequency range. The delay time is dependent and accomplished by a variable bias voltage. Attention is focussed on the fact that the topology will be implemented taking into account low-voltage and low-power. The CMOS (complementary metal oxide semiconductor) circuit design is based on the G m − C low-pass linear integrator as the main core. This way, a delay line circuit with two taps was implemented in a 1.2-μm CMOS technology. The experimental results show a spurious free dynamic range of 56 dB, a total harmonic distortion of 0.56% and power dissipation of 52 μW with a supply voltage of 1.5 V.

Synthesis of 1-Input 3-Output Optical Delay-Line Circuit with IIR Architectures

The synthesis algorithm is presented for 1-input 3-output optical delay-line circuit with IIR architectures. The authors recently reported circuit structure and subsequent synthesis algorithm for r 1x3optical delay-line circuit that can realize any arbitrary frequency characteristics of FIR optical filters. In the present paper, circuit configuration and synthesis mechanism for 1x3optical delay-line circuit with ring waveguides is proposed that can realize similar filter characteristics as infinite impulse response (IIR) digital filters. The Synthesis algorithm is based on division of the total transfer matrix into basic unit blocks. A three-port IIR optical filter has been synthesized using the design data of IIR digital filter. In addition, in this article recent patents are also discussed. Keywords: Optical delay-line circuit, finite impulse response (FIR) filter, infinite impulse response (IIR) filter etc

A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm

Most signals between chips or packages in an electric circuit board require certain delays in order to achieve good timing. An extension of the circuit line that is proportional to the designated time delay has been a usual practice due to cost effectiveness. However, the layout of the line becomes dense due to the small size of packages or circuit boards, and this generates crosstalk, causing signal detection errors. In this paper, a design methodology of delay line layout for crosstalk minimization is developed using the genetic algorithm (GA). The GA requires a large number of function evaluations, and efficient calculation of crosstalk is proposed together with a new technique of generating random line, making offsprings, and mutation. Different optimum results have been obtained for different objectives and compared. Some of the designs were actually manufactured and experimentally tested, showing the validity of the optimum results.

Tolerance Analysis of Lattice-Form Optical Interleaver With Different Coupler Structures

A set of recursion equations is developed to synthesize a coherent two-port lattice-form optical delay-line circuit with different coupler structures. A fifth-order lattice-form optical interleaver is designed, and parameter tolerance is analyzed with crosstalk consideration. Results show that the phase tolerance of delay lines is six times the coupling-coefficient-angle tolerance of directional couplers. The coupling-coefficient-angle tolerance of directional couplers in an interleaver with stabilized couplers is improved by one order than that in an interleaver with simple directional couplers if global uniformity of the planar-lightwave-circuit process is supposed. The tolerance of an interleaver with cascaded multimode interference (MMI) couplers does not improve much, but an MMI coupler is more immune to process error than a directional coupler. Theoretical analysis meets the simulation results well. A stabilized coupler and a cascaded MMI coupler are both good substitutes for a simple directional coupler in lattice-form optical interleaver, and both help to reduce crosstalk

An ASK Modulator and Antenna Driver for 13.56 MHz RFID Readers and NFC Devices

We propose an ASK modulator and Antenna driver for multi-standard 13.56MHz RFID readers and NFC devices. The proposed transmitters of RFID readers and NFC devices consist of ASK modulator, inverting output driving buffer and off-chip antenna with a matching circuit. The ASK modulation depth can easily be controlled by adjusting duty ratio by the delay line circuit. The test chip was fabricated by using a 0.35μm double poly CMOS process. The measured results demonstrated that the proposed circuit has met the standard specifications.