New topology for a variable differential delay line using the FGMOS transistor

Abstract

In this study, we show that floating gate MOS (metal oxide semiconductor) transistors support a low-voltage and low-power variable analogue differential delay line circuit for signals in the audio frequency range. The delay time is dependent and accomplished by a variable bias voltage. Attention is focussed on the fact that the topology will be implemented taking into account low-voltage and low-power. The CMOS (complementary metal oxide semiconductor) circuit design is based on the G m − C low-pass linear integrator as the main core. This way, a delay line circuit with two taps was implemented in a 1.2-μm CMOS technology. The experimental results show a spurious free dynamic range of 56 dB, a total harmonic distortion of 0.56% and power dissipation of 52 μW with a supply voltage of 1.5 V.