Delay-insensitive Circuits Research Articles

Transistor Count Reduction Technique for Clockfree Null-convention Arithmetic Logic Circuits

Null Convention Logic (NCL) is a robust clock-less technique for designing asynchronous delay-insensitive circuits. The traditional complementary metal oxide semiconductor (CMOS) approach is often used for designing NCL circuits, which tends to occupy a large area. To address this issue, a low power design technique Gate Diffusion Input (GDI) is introduced for designing the NCL circuits. This GDI design methodology is the promising alternative for the static CMOS designs, which allows the reduction in area and power consumption while maintaining the low complexity of the logic design. In this paper, a novel GDI based NCL designs are proposed and designed. However, the voltage swings in the GDI approach leads to the considerable amount of voltage drop at the output. This limitation is addressed by using low threshold transistors where a voltage drop is expected, and high threshold transistors are used for the regenerative inverters at the output. The proposed approach has been verified by designing the NCL Ripple Carry Adder (RCA), Unpipelined multiplier, pipelined multiplier and Unpipelined ALU by using the GDI technique. These models are designed and simulated using Cadence Virtuoso and an average of 13.5 % reduction in the transistor count is observed for these GDI based NCL models when compared to the CMOS models.

THE OPTIMIZATION OF ENERGY-EFFICIENCY AND RELIABILITY USING COMPLEX REDUNDANCY IN COMPUTING SYSTEMS

Context. The increase of energy-efficiency and reliability of computing systems is still important task in 21st century. It is especially important in the field of computing systems for aerospace because both the radiation-tolerance should be provided and the energy-consumption are very limited. Moreover, the developers should take care about performance of a computing system. Therefore, all of this result in difficult optimization task with key-parameters – reliability, energy-efficiency and performance in conditions of existing technologies limits. Objective. The solution of optimization task – the synthesis of digital devices that can work in wide temperature and voltage range at restrictions on reliability probability and performance. Method. Delay-insensitive (or Self-timed according to Russian terms) circuits can stable operate in delay variation including operation under ultra-low-supply-voltage (ULSV). That is why it became a good solution for considered task. To increase reliability in the critical fields of application, the redundancy is often used. For example, the triple modular redundancy or the Hamming codes. However, the implementing of these methods in delay-insensitive circuits faces problems – excessive increase of complexity or delays in critical paths. In addition, the Muller’s model are not provide possibilities to take into account failures as normal part of system operations. Thus, the definitions of fault-tolerance and semi-modularity (the basic feature of delay-insensitive circuits) have a conflict. In the paper the method of redundancy at transistor level was developed. The combination of proposed and known methods allows receiving new efficient solutions. Results. The model of fault-tolerant self-timed circuits was developed. The method of complex redundancy for self-timed circuits was proposed. This method provides synthesis of digital devices with optimization in key parameters. Conclusions. The research proved that only the combination of methods provide the achievement of function’s optimum. It is interesting task to expand the object of research to synchronous and globally asynchronous locally synchronous computing systems in further research.

A universal Brownian cellular automaton with 3 states and 2 rules

This paper presents a 3-state asynchronous CA that requires merely two transition rules to achieve computational universality. This universality is achieved by embedding Priese’s delay-insensitive circuit elements, called the E-element and the K-element, on the cell space of a so-called Brownian CA, which is an asynchronous CA containing local configurations that conduct a random walk in the circuit topology.

Modeling and Comparing of Dual Rail Delay Insensitive Circuit Architecture

Modeling and Comparing of Dual Rail Delay Insensitive Circuit Architecture

새로운 고속의 NCL 셀 기반의 지연무관 비동기 회로 설계

새로운 고속의 NCL 셀 기반의 지연무관 비동기 회로 설계

Low-Power Asynchronous NCL Pipelines With Fine-Grain Power Gating and Early Sleep

null convention logic (NCL) is a promising design paradigm for constructing asynchronous delay-insensitive circuits. This brief presents two novel NCL pipeline structures, called fine-grain power gating NCL with early sleep (FPG-NCL-ES) and fine-grain power gating NCL with early sleep and optimization (FPG-NCL-ES-OPT), which employ both fine-grain power gating and early sleep to achieve lower power consumption. With fine-grain power gating, a logic block in FPG-NCL-ES becomes active only when performing useful work and is power gated to reduce leakage power when inactive. Moreover, with the early sleep mechanism, the multithreshold CMOS (MTCMOS) threshold gates in a pipeline stage can enter the sleep mode early once the data output of this stage has been received by the downstream pipeline stage, without waiting for the next null wavefront to arrive at this stage. Thus, the MTCMOS threshold gates in the FPG-NCL-ES pipeline have a higher probability of staying in the sleep mode than those in the traditional power-gated NCL pipeline. A modified asymmetric C-element is proposed to replace the traditional C-element for supporting early sleep. The FPG-NCL-ES-OPT pipeline employs a circuit simplification to further reduce silicon area and power consumption. Simulation results show that, compared with the traditional NCL counterpart, the FPG-NCL-ES-OPT implementation of the Kogge–Stone adder can achieve a higher maximum sustainable throughput rate, lower power consumption, and lower hardware cost.

Emergence of universal global behavior from reversible local transitions in asynchronous systems

Reversible computing usually focuses on how to establish a valid equivalence between the global reversibility and local reversibility in computational systems. Hitherto the equivalence has been precisely developed in cellular automata, combinational circuits and quantum computers, but it implicitly assumes that the underlying systems are synchronously timed. Alternative systems include the delay-insensitive (DI) circuits and asynchronous cellular automata (ACAs), where the local operations of each component (cell) may be executed independently at random times. Despite the randomness associated with asynchronous timings, equivalence between the global and local reversibility can be simply achieved in both DI-circuits (Morita, 2001) and ACAs (Lee et al., 2003), provided that their local operations (transitions) are thoroughly serialized. The complete exclusion of concurrency in local behavior, however, will profoundly depress the parallel processing efficiency of DI-circuits as well as the intrinsic massive parallelism of ACAs. This paper aims at exploring what kind of complex global behavior may arise from the concurrent operations that are invertible at local level. To this end, we show that DI-circuits composed of reversible elements can actually exhibit universal input and output behavior, with the universality emerging from the concurrency in reversible local operations. Likewise, by further embedding all circuits into the cellular space, the emergence of universal global transitions from reversible local transitions can be exactly identified in an ACA which, due to the bijectivity of its local function, has significantly lower complexity as compared to other models.

Paired T‐element design for multiple‐state acknowledge dependency

A paired T-element that assists in successfully controlling a dual-rail delay-insensitive asynchronous circuit system that implements multiple states containing acknowledge networks, that are interdependent, is presented. A T-element allows triggering of next-state actions concurrently with negation of its acknowledge input. However, this introduces a timing assumption that can cause system failure if it is violated. With little additional overhead, the paired T-element is designed to combine the functionality of two standard T-elements and allow adjacent reads to take place when there are inter-state dependencies. This component successfully overlaps advantages of the performance optimisation of the original T-element with the safety of the solution to this control scenario, making it an important element to be used in dual-rail delay-insensitive asynchronous circuit systems.

Relativistic Causality and Clockless Circuits

Time plays a crucial role in the performance of computing systems. The accurate modelling of logical devices, and of their physical implementations, requires an appropriate representation of time and of all properties that depend on this notion. The need for a proper model, particularly acute in the design of clockless delay-insensitive (DI) circuits, leads one to reconsider the classical descriptions of time and of the resulting order and causal relations satisfied by logical operations. This questioning meets the criticisms of classical spacetime formulated by Einstein when founding relativity theory and is answered by relativistic conceptions of time and causality. Applying this approach to clockless circuits and considering the trace formalism, we rewrite Udding’s rules, which characterize communications between DI components. We exhibit their intrinsic relation with relativistic causality. For that purpose, we introduce relativistic generalizations of traces, called R-traces, which provide a pertinent description of communications and compositions of DI components.

Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime

The quadratic relationship between power consumption and supply voltages encourages digital circuits to work in subthreshold regime for low- to mid-speed applications. While working under nearand sub-threshold, quasi-delay-insensitive (QDI) asynchronous circuits have the added advantages including highly robust operation and automatic adaptivity to supply voltage changes without external control/adjustment or timing analysis. This paper presents two optimization methods for QDI asynchronous circuits under subthreshold for further energy reduction: threshold voltage adjustment through body biasing to achieve minimum energy consumption at given speed requirements, and balanced gate design topology to ensure circuit’s proper functioning under deep-subthreshold supply voltages. While the former enables QDI asynchronous circuits to consume optimal energy while satisfying performance requirements, the latter allows QDI asynchronous circuits to directly interface with energy harvesting and analog components, whose voltages are usually much lower than designated digital supply voltage, thereby removing the need of additional voltage translating circuits. Both methods have been demonstrated through a QDI asynchronous ALU designed using the NULL Convention Logic (NCL).

Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delay-insensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach proposed in this paper the circuit expressions corresponding to a design are first converted into Reed---Muller forms and then implemented using delay-insensitive Reed---Muller cells. The design and layout of the Reed---Muller cell using primitives has been described in detail. The effects of stuck-at faults in both delay-insensitive primitives and gates have been analyzed. Since circuits implemented in Reed---Muller forms constructed by the Reed---Muller cells can be easily tested offline, the proposed approach for delay-insensitive circuit design improves a circuit's testability. Potential physical implementation of cellular arrays and its area overhead are also discussed.

Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits

We consider the problem of synthesizing the asynchronous wrappers and glue logic needed for the correct GALS implementation of a modular synchronous system. Our approach is based on the weakly endochronous synchronous model, which defines high-level, implementation-independent conditions guaranteeing correct desynchronization at the level of the abstract synchronous model. We can therefore factor the synthesis problem into (1) a high-level, implementation-independent phase insuring the weak endochrony of each synchronous module and (2) the actual wrapper synthesis phase, highly simplified by the high-level assumptions, yet flexible enough to produce various, efficient implementations.We focus here on the synthesis of delay-insensitive asynchronous wrappers from weakly endochronous synchronous modules, and show how this can be done for a simple DLX processor model.

Universal delay-insensitive systems with buffering lines

A delay-insensitive (DI) circuit is a type of asynchronous circuit that is robust to arbitrary delays in circuit elements or interconnection lines. This paper presents a new class of DI circuits of which interconnection lines have buffers that may contain multiple signals. We propose a set of three primitive circuit elements each of which has at most four lines for input or output. We prove that this set can be used to construct all valid DI circuits with buffering lines, i.e., that it is universal. Two more sets of three primitives with connectivity four are also presented, and their universality is shown. The limited number of primitives required in each universal set and the low connectivity of the primitives, as compared to previously proposed DI circuits, may facilitate efficient implementation of DI circuits in nanocomputer architectures based on asynchronous cellular automata.

Early evaluation for performance enhancement in phased logic

Data-dependent completion time is a well-known advantage of self-timed circuits, one that allows them to operate at average rather than worst-case execution rates. A technique called early evaluation (EE) that extends this advantage by allowing self-timed modules to produce results before all of their inputs have arrived is described here. The technique can be applied to any combinational function and is integrated into the phased logic (PL) design methodology that accepts synchronous design entry and produces delay-insensitive self-timed circuits. We describe an algorithm that ensures that the resulting delay-insensitive circuits are safe, and develop a generalized method for inserting EE gates into any PL netlist. We give performance results for several benchmark circuits, including a five-stage pipelined CPU and a microprogrammed floating-point unit. Comparisons are made among clocked circuits, PL circuits, and PL circuits with EE. Simulation results show a clear performance benefit for PL circuits that use EE.

Delay-insensitive computation in asynchronous cellular automata

Asynchronous cellular automata (ACA) are cellular automata that allow cells to update their states independently at random times. Because of the unpredictability of the order of update, computing on ACA is usually done by simulating a timing mechanism to force all cells into synchronicity after which well-established synchronous methods of computation can be used. In this paper, we present a more effective method of computation based upon a 4-state two-dimensional ACA with von Neumann neighborhood that is based on the construction in the cellular space of delay-insensitive circuits, a special type of asynchronous circuits, whose operations are robust to arbitrary delays in operators or interconnection lines. We show that this novel ACA model can be used to construct a universal Turing machine, which suffices to prove its computational universality.

Universal delay-insensitive circuits with bidirectional and buffering lines

Delay-insensitive (DI) circuits are a class of asynchronous circuits whose correctness of operation is robust to arbitrary delays in modules or interconnection lines. Keller clarified the precise operating conditions of the class of DI-circuits and presented a universal set of primitive modules from which any circuit in the class is realizable. Later, Patra and Fussell presented an alternative universal set of primitive modules and claimed that there is no universal set of primitives satisfying Keller's conditions in which the largest number of input and output lines of each primitive module is less than five. We present new types of primitive modules, each having at most three input and output-lines and show they form a universal set of primitives. We achieve this reduction in complexity by allowing the input and output-lines of modules to be bidirectional and to be able to buffer signals. The use of buffers in interconnection lines allows higher throughput of signals and results in circuits requiring less feedback lines, thus improving the efficiency of DI-circuits. The proposed class of Dl-circuits is especially useful for implementations on cellular automata - an architecture that promises efficient implementations and manufacturing in nanotechnology due to its regular structure.

Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

The modelling of delay-insensitive asynchronous circuits in the process calculus CCS is addressed. MUST-testing (rather than bisimulation) is found to support verification both of the property of delay-insensitivity and of design by stepwise refinement. Automated verification is possible with a well-known tool, the Edinburgh Concurrency Workbench.

Computation by Asynchronously Updating Cellular Automata

A known method to compute on an asynchronously updating cellular automaton is the simulation of a synchronous computing model on it. Such a scheme requires not only an increased number of cell states, but also the simulation of a global synchronization mechanism. Asynchronous systems tend to use synchronization only on a local scale—if they use it at all. Research on cellular automata that are truly asynchronous has been limited mostly to trivial phenomena, leaving issues such as computation unexplored. This paper presents an asynchronously updating cellular automaton that conducts computation without relying on a simulated global synchronization mechanism. The two-dimensional cellular automaton employs a Moore neighborhood and 85 totalistic transition rules describing the asynchronous interactions between the cells. Despite the probabilistic nature of asynchronous updating, the outcome of the dynamics is deterministic. This is achieved by simulating delay-insensitive circuits on it, a type of asynchronous circuit that is known for its robustness to variations in the timing of signals. We implement three primitive operators on the cellular automaton from which any arbitrary delay-insensitive circuit can be constructed and show how to connect the operators such that collisions of crossing signals are avoided.

Laying out circuits on asynchronous cellular arrays: a step towards feasiblenanocomputers?

Opinions differ widely as to the type of architecture most suitable forachieving the tremendous performance gains expected with computersbuilt by nanotechnology. In this context little research effort has goneinto asynchronous cellular arrays, an architecture that is promising fornanocomputers due to (1) its regular structure of locally interconnected cells,and (2) its asynchronous mode of timing. The first facilitates bottom-upmanufacturing techniques like directed self-assembly. The second allows thecells’ operations to be timed randomly and independently of each other,mitigating the problems accompanying a central clock, like high powerconsumption and heat dissipation. The advantages of asynchronous timingnotwithstanding, it makes computation less straightforward. Attemptsto compute on asynchronous cellular arrays have therefore focused onsimulating synchronous operation on them, at the price of more complex cells.Here we advance a more effective approach based on the configurationon an asynchronous cellular array of delay-insensitive circuits, a type ofasynchronous circuit that is robust to arbitrary delays in signals. Ourresults may be a step towards future nanocomputers with a huge numberof autonomously operating cells organized in homogeneous arrays thatcan be programmed by configuring them as delay-insensitive circuits.

Verified compilation of communicating processes into clocked circuits

Abstract We have previously developed a verified algorithm for compiling programs written in an occam-like language into delay-insensitive circuits. In this paper we show how to retarget our compiler for clocked circuits. Since verifying a hardware compiler is a huge effort, it is significant that we are able to retarget our compiler proof without recreating that effort. The chief contribution of this paper is the methodology used for retargeting our compiler which is based upon a new model for systems with both synchronous and asynchronous behaviour. The retargeting proof utilizes both theorems proved algebraically by hand and theorems proved automatically by state exploration. The technique of protocol conversion is used extensively in modularizing the proof of the clocked implementation.