Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

Hemangee K Kapoor,Mark B Josephs

doi:10.1016/j.ipl.2003.12.007

Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench

Hemangee K Kapoor, Mark B Josephs

https://doi.org/10.1016/j.ipl.2003.12.007

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Journal: Information Processing Letters	Publication Date: Jan 22, 2004
Citations: 16

Affiliation: London South Bank University

#Concurrency Workbench #Stepwise Refinement + Show 7 more

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Abstract

The modelling of delay-insensitive asynchronous circuits in the process calculus CCS is addressed. MUST-testing (rather than bisimulation) is found to support verification both of the property of delay-insensitivity and of design by stepwise refinement. Automated verification is possible with a well-known tool, the Edinburgh Concurrency Workbench.

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