Delay Degradation Research Articles

Nanocomposites Based on Cassava Starch and Chitosan-Modified Clay: Physico‑Mechanical Properties and Biodegradability in Simulated Compost Soil

Organic-inorganic nanocomposites based on cassava starch, glycerol and chitosan-modified Veegum® HS clay mineral at two different low polymer-to-clay ratios (2.5 and 5.0 wt.%) were prepared by extrusion producing flexible, transparent and homogeneous plastics as potential candidates for agricultural purposes. X-ray diffraction and transmission electron microscopy images revealed the presence of both intercalated and exfoliated nanocomposites in all samples, in which exfoliation is the predominant type of microscopic structure. Statistically significant improvements of over 20% on the tensile strength and Young's modulus were observed for samples containing chitosan-modified clay in comparison to pristine thermoplastic starch. Chitosan deeply affects the conversion of polymer carbon to CO2 through biodegradation. Mineralization values for the sample loaded with 5.0 wt.% of chitosan-modified clay in simulated compost soil showed a reduction of almost 40% in comparison to thermoplastic starch, benefiting applications where delay degradation is required.

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability

An efficient temperature dependent hot carrier injection reliability simulation flow

This paper presents an efficient temperature dependent hot carrier injection reliability simulation flow which is scalable. The flow makes use of some efficient techniques at different design hierarchical levels to enable full chip simulation with a fast run time and high enough accuracy. While the transistor-level HCI effect is modeled based on the conventional reaction–diffusion (R–D) framework, the gate-level characterization method combines HSpice simulation and piecewise linear curve fitting to model the impact of HCI effect over the time. Also, as one of the ways to improve the speed of the simulation, only the NMOS transistors, which suffer much more from the HCI effect, are considered in the modeling. In addition, among these devices, only those which are more significantly affected are included. For each cell, only the transitions which induce the HCI impact are included. Finally, to improve the efficiency of the circuit simulation, logic cells in the circuit are classified into two groups of critical and non-critical where the critical (non-critical) ones are simulated using fine (coarse) granularity simulation time steps. The proposed method reduces the simulation time without losing much of accuracy. Also, due to the considerable impact of the temperature on the reliability, at all levels of the proposed simulation flow, the impact of the temperature on the impact of the HCI phenomena is modeled. The simulations performed on some benchmarks reveal that the proposed circuit-level HCI modeling is able to reduce the runtime of calculating the threshold voltage and mobility drifts of the gates significantly without sacrificing accuracy unacceptably. Also, the circuit-level simulations indicate an about 19% increase in the average of the HCI-induced delay degradation of the benchmarks when the temperature rises from 20°C to 100°C.

Unfaithful Glitch Propagation in Existing Binary Circuit Models

We show that no existing continuous-time, binary value-domain model for digital circuits is able to correctly capture glitch propagation. Prominent examples of such models are based on pure delay channels (P), inertial delay channels (I), or the elaborate Delay Degradation Model (DDM) channels proposed by Bellido-Diaz et al. We accomplish our goal by considering the border between solvability and non-solvability of a simple problem called short-pulse filtration (SPF), which is closely related to arbitration and synchronization. On one hand, we prove that SPF is solvable in bounded time in any such model that provides channels with non constant delay, like I and DDM. This is in opposition to the impossibility of solving bounded SPF in real (physical) circuit models. On the other hand, for binary circuit models with constant-delay channels, we prove that SPF cannot be solved even in unbounded time; again in opposition to physical circuit models. Consequently, indeed none of the binary value-domain models proposed so far (and that we are aware of) faithfully captures glitch propagation of real circuits. We finally show that these modeling mismatches do not hold for the weaker eventual SPF problem.

Improving speed of tunnel FETs logic circuits

Tunnel transistors are one of the most attractive steep subthreshold slope devices which are being investigated to overcome power density and energy inefficiency exhibited by CMOS technology. These transistors exhibit asymmetric conduction which can cause sustained noise voltage pulses (bootstrapping) within digital tunnel FET circuits leading to delay degradation. A minor modification of the complementary gate topology to avoid the bootstrapping problem is proposed and its impact on speed at the circuit level is shown. Speed improvements up to 33% have been obtained for 8-bit ripple carry adders when implemented with the solution.

An early congestion feedback and rate adjustment schemes for many-to-one communication in cloud-based data center networks

Cloud data centers are playing an important role for providing many online services such as web search, cloud computing and back-end computations such as MapReduce and BigTable. In data center network, there are three basic requirements for the data center transport protocol such as high throughput, low latency and high burst tolerance. Unfortunately, conventional TCP protocols are unable to meet the requirements of data center transport protocol. One of the main practical issues of great importance is TCP Incast to occur many-to-one communication sessions in data centers, in which TCP experiences sharp degradation of throughput and higher delay. This important issue in data center networks has already attracted the researchers because of the development of cloud computing. Recently, few solutions have been proposed for improving the performance of TCP in data center networks. Among that, DCTCP is the most popular protocol in academic as well as industry areas due to its better performance in terms of throughput and latency. Although DCTCP provides significant performance improvements, there are still some defects in maintaining the queue length and throughput when the number of servers is too large. To address this problem, we propose a simple and efficient TCP protocol, namely NewDCTCP as an improvement of DCTCP in data center networks. NewDCTCP modified the congestion feedback and window adjusting schemes of DCTCP to mitigate the TCP Incast problem. Through detailed QualNet experiments, we show that NewDCTCP significantly outperforms DCTCP and TCP in terms of goodput and latency. The experimental results also demonstrate that NewDCTCP flows provide better link efficiency and fairness with respect to DCTCP.

Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits

In this work, we investigate the co-dependency of die temperature and bias temperature instability (BTI) and their combined effect on the lifetime of VLSI circuits. The investigation considers the impact of die temperature in increasing the effect of the BTI as well as changes in the die temperature due to the BTI-induced threshold voltage alterations. In addition, the impact of workloads on the degree of the BTI-induced degradation in VLSI circuits is studied. This impact accounts for the direct influence of the signal probability of the internal nodes under the given workload as well as its indirect influence due to power consumption and temperature changes of the circuits. The study is performed by using a simulation framework that captures dynamic changes in the operating temperature and application workload. Simultaneous consideration of the dynamic workload and operating temperature enables one to accurately predict the circuit lifetime. To assess the accuracy of the proposed approach, the estimated delay degradations caused by the Negative BTI (NBTI) for some large circuits from ISCAS'89 and ITC'99 benchmark suites when circuits are simulated under dynamic (both temperature and workload are updated periodically), semi-static (either temperature or workload is updated periodically), and static (no updating is performed) scenarios are compared. Simulation results obtained in a 45nm CMOS technology, reveal that the predicted timing degradation in the case of the dynamic scenario is significantly different than those of the other scenarios. The differences ranged from −135% to +98% for the considered circuits in this work. The large differences demonstrate that for accurate estimation of the circuit lifetime under the BTI effect, the dynamic scenario should be adopted as part of the standard design flows.

Performance Evaluation of Energy Efficient Packet Transmissions Considering Fairness for Wi-Fi System

Wi-Fi STAs in power saving mode described in the Wi-Fi specification can deteriorate the system performance such as throughput, time delay when they receive data frames from a Wi-Fi AP. This problem is caused by data frame reception failure due to the channel state, and it increases re-transmissions. In this paper, we propose a modified power saving mode considering fairness of Wi-Fi system in order to solve the problem. By simulation, we showed that data throughput can be increased without time delay degradation if the proposed method restricting the number of packet transmission attempts and HARQ are used.

FD-AQM: Fairness-Aware Delay-Controlled Active Queue Management in 802.11s-Based Multi-Radio Multi-Channel Wireless Mesh Networks

Several active queue management (AQM) schemes have been proposed to address the bufferbloat issue, a long network delay and performance degradation issue caused by excess buffering of packets in network nodes. The solutions proposed up to now, however, satisfy only a subset of the key network performance metrics, i.e., end-to-end throughput, throughput fairness, and delay, in 802.11s-based multi-radio multi-channel wireless mesh networks (MRMC WMN). In this letter, we propose FD-AQM, a fairness-aware delay-controlled AQM to satisfy all three key network performance metrics simultaneously in the 802.11s-based MRMC WMN. The proposed FD-AQM achieves the goal by adopting a per-queue drop interval which is recalibrated according to the average round-trip time of flows, and a drop decision mechanism which considers average throughput as well as target delay. Through simulations, we show that FD-AQM is superior to other AQM schemes in terms of throughput and fairness.

On-Chip Delay Degradation Measurement for Aging Compensation

As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stress conditions such as Negative-Bias-Temperature Instability (NBTI) and Hot-Carrier-Injection (HCI). Hence, this paper proposes a novel on-chip circuit to measure the delay degradation of stressed MOSFET digital circuits and digitalize the degradation for aging compensation. A 0.11μm CMOS technology has been used to implement and evaluate the proposed circuits. Keywords: Aging Effect, Aging Prediction, Bias Temperature Instability, Hot Carrier Injection, Reliability

Riboflavin-induced photo-crosslinking of collagen hydrogel and its application in meniscus tissue engineering.

A meniscus tear is a common knee injury, but its regeneration remains a clinical challenge. Recently, collagen-based scaffolds have been applied in meniscus tissue engineering. Despite its prevalence, application of natural collagen scaffold in clinical setting is limited due to its extremely low stiffness and rapid degradation. The purpose of the present study was to increase the mechanical properties and delay degradation rate of a collagen-based scaffold by photo-crosslinking using riboflavin (RF) and UV exposure. RF is a biocompatible vitamin B2 that showed minimal cytotoxicity compared to conventionally utilized photo-initiator. Furthermore, collagen photo-crosslinking with RF improved mechanical properties and delayed enzyme-triggered degradation of collagen scaffolds. RF-induced photo-crosslinked collagen scaffolds encapsulated with fibrochondrocytes resulted in reduced scaffold contraction and enhanced gene expression levels for the collagen II and aggrecan. Additionally, hyaluronic acid (HA) incorporation into photo-crosslinked collagen scaffold showed an increase in its retention. Based on these results, we demonstrate that photo-crosslinked collagen-HA hydrogels can be potentially applied in the scaffold-based meniscus tissue engineering.

Backoff Design for IEEE 802.11 DCF Networks: Fundamental Tradeoff and Design Criterion

Binary Exponential Backoff (BEB) is a key component of the IEEE 802.11 DCF protocol. It has been shown that BEB can achieve the theoretical limit of throughput as long as the initial backoff window size is properly selected. It, however, suffers from significant delay degradation when the network becomes saturated. It is thus of special interest for us to further design backoff schemes for IEEE 802.11 DCF networks that can achieve comparable throughput as BEB, but provide better delay performance. This paper presents a systematic study on the effect of backoff schemes on throughput and delay performance of saturated IEEE 802.11 DCF networks. In particular, a backoff scheme is defined as a sequence of backoff window sizes $\{W_{i}\}$ . The analysis shows that a saturated IEEE 802.11 DCF network has a single steady-state operating point as long as $\{W_{i}\}$ is a monotonic increasing sequence. The maximum throughput is found to be independent of $\{W_{i}\}$ , yet the growth rate of $\{W_{i}\}$ determines a fundamental tradeoff between throughput and delay performance. For illustration, Polynomial Backoff is proposed, and the effect of polynomial power $x$ on the network performance is characterized. It is demonstrated that Polynomial Backoff with a larger $x$ is more robust against the fluctuation of the network size, but in the meanwhile suffers from a larger second moment of access delay. Quadratic Backoff (QB), i.e., Polynomial Backoff with $x=2$ , stands out to be a favorable option as it strikes a good balance between throughput and delay performance. The comparative study between QB and BEB confirms that QB well preserves the robust nature of BEB and achieves much better queueing performance than BEB.

Design of High-Speed Energy-Efficient Masking Error Immune PentaMTJ-Based TCAM

The main challenge in ternary content addressable memory (TCAM) design is to reduce the power consumption associated with searching without the increase in delay. This paper proposes a novel PentaMTJ-based TCAM and then compares its delay and power consumption with the previously reported MTJ-based TCAM. TCAM is comprised of PentaMTJ cell, which is used for the storage of information, and a precharge sense amplifier (PCSA) for its sensing. A VerilogA model of the PentaMTJ along with 45 nm CMOS technology is used for the simulation. A power reduction of 17.64 times with minor delay degradation of 1.081 times is obtained compared with previously reported TCAMs. This leads to power delay product improvement of 16.38 times for 576 b TCAM.

Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits

This paper focuses on hot-carrier effects in modern CMOS technologies and proposes a scalable method for analyzing circuit-level delay degradations in large digital circuits, using methods that take abstractions up from the transistor to the circuit level. We begin with an exposition of our approach for the nominal case. At the transistor level, a multimode energy-driven model for nanometer technologies is employed. At the logic cell level, a methodology that captures the aging of a device as a sum of device age gains per signal transition is described, and the age gain is characterized using SPICE simulation. At the circuit level, the cell-level characterizations are used in conjunction with probabilistic methods to perform fast degradation analysis. Next, we extend the nominal case analysis to include the effect of process variations. Finally, we show the composite effect of these approaches in the presence of other aging variations, notably bias temperature instability, and study the relative impact of each component of aging on the temporal trends of circuit delay degradations. The analysis approaches for nominal and variational cases are both validated by Monte Carlo simulation on various benchmark circuits, and are proved to be accurate, efficient, and scalable.

Sleeping mobile AP: a novel energy efficient Wifi tethering scheme

Wifi tethering enables Wifi-only devices to access the Internet by sharing the WWAN (e.g., 3G and LTE) connection of a smartphone where there is no available Wifi access point. However, the current tethering schemes have a limitation as they consume a significant portion of the battery power for providing Wifi clients with the Internet connection. In this paper, we propose a new tethering scheme that reduces the energy consumption of a mobile AP (MAP) without substantial throughput and delay degradation. To improve energy efficiency, the proposed scheme adaptively adjusts the sleep and wake-up periods based on the bandwidth asymmetric feature of the MAP. Further, it provides a longer idle time enough to put the clients into a sleep mode by combining idle periods between subsequent packets, and conserves their energy as well. Our evaluation based on the prototype implementation on commercial smartphones shows that the proposed scheme reduces the energy consumption of the MAP and the client smartphones by up to 56.0 and 8.3 %, respectively.

Time domain analysis of the physical wiring for a star-like topology in high-speed controller area networks

The high-speed controller area network protocol supports a linear wiring topology. However, owing to productivity and cost concerns, actual networks in automotive applications may be configured in a star-like topology using joint connectors, with multiple stubs diverging from one point on the main bus; this type of configuration may lead to increased signal reflection and requires careful design of the physical wiring. In this study, the time response in a star-like joint-connector-based controller area network bus topology is analysed, and design guidelines for the physical wiring are presented. The effects of the number of stubs connected to a joint connector on the signal transmission are described and evaluated through experiments. Then, the time response through a joint connector with a diverse number of stubs is estimated, which gives a timing reference for designing the physical wiring in a star-like bus topology. Additionally, the effects of reflection between adjacent joint connectors are analysed together with the distance between joint connectors to ensure that no propagation delay degradation occurs.

Monitoring of aging in integrated circuits by identifying possible critical paths

Aging of integrated circuits can no longer be neglected in advanced process technologies. Especially the strong dependence of the delay degradation of digital circuits on the workload is still an unsolved problem. If the workload is not known exactly, only a worst-case design can guarantee that the circuit works correctly during the entire specified lifetime. We propose a method that enables a better-than-worst-case design. To assure that this design still works correctly during the specified lifetime, the circuit is monitored periodically and countermeasures are taken if the circuit degrades too much. Our main contribution is an algorithm to identify all paths that might become critical during the specified lifetime. These are called possible critical paths (PCPs). This is the first approach that also considers local process variations for finding the PCPs. Without considering process variations, it is not guaranteed that all possible critical paths are found. In addition, we could reduce the number of paths that have to be monitored by 2.7× compared to a state-of-the-art approach.

NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time

SUMMARY Negative Bias Temperature Instability (NBTI) is one of the serious concerns for long-term circuit performance degradation. NBTI degrades PMOS transistors under negative bias, whereas they recover once negative bias is removed. In this paper, we propose a mitigation method for NBTI-induced performance degradation that exploits the recovery property by shifting random input sequence through scan paths. With this method, we prevent consecutive stress that causes large degradation. Experimental results reveal that random scan-in vectors successfully mitigate NBTI and the path delay degradation is reduced by 71% in a test case when standby mode occupies 10% of total time. We also confirmed that 8-bit LFSR is capable of random number generation for this purpose with low area and

NBTI-aware circuit node criticality computation

For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable effort on accurate modeling and characterization of circuit delay degradation caused by NBTI at different design levels. The search for techniques and methodologies which can aid in effectively minimizing the NBTI effect on circuit delay is still underway. In this work, we present the usage of node criticality computation to drive NBTI-aware timing analysis and optimization. Circuits that have undergone this optimization flow show strong resistance to NBTI delay degradation. For the first time, this work proposes a node criticality computation algorithm under an NBTI-aware timing analysis and optimization framework. Our work provides answers to the following yet unaddressed questions: (a) what is the definition of node criticality in a circuit under the NBTI effect? (b) how do we identify the critical nodes that, once protected, will be immune to NBTI timing degradation? and (c) what are the NBTI effect attenuation approaches? Experimental results indicate that by protecting the critical nodes found by our proposed methodology, circuit delay degradation can be reduced by up to 50%. Combined with peak temperature reduction, the delay degradation can be be further improved.

Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution-based analysis. The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.