Delay Block Research Articles

Fault diagnosis and fault‐tolerant control of uncertain network control systems

SummaryIn this article, the equivalent control strategy based on Laplace transform is proposed for the problem of stochastic delay in networked control systems. The original system is transformed into an equivalent control system without random delay block by Laplace transform. Then, a new augmented variable and equivalent control system is introduced to construct an augmented system. An adaptive fault diagnosis observer is designed based on the augmented system. The adaptive turning rate of the observer is obtained by solving the corresponding linear matrix inequality. Based on the information of online fault diagnosis and state estimation, a fault‐tolerant controller based on PI control strategy is designed to compensate the fault. Finally, a model of the switched reluctance motor system is considered to show the effectiveness of this method.

Frequency delay‐dependent stability criterion for time‐delay systems thanks to Fourier–Legendre remainders

AbstractThis paper investigates the stability of a linear finite‐dimensional system interconnected to a single delay operator. From robust approaches, to derive delay‐dependent frequency tests, a characterization of the delay behavior is required. Based on approximation methods, one describes the transported signal by lumped parameters. More precisely, by the use of the first Fourier–Legendre polynomials coefficients, we split the delay block into a finite‐dimensional part interconnected to a specific infinite‐dimensional residual part. Two models are investigated with residuals related to two Fourier–Legendre remainders of the delayed transfer function. The main contribution is to highlight that the finite‐dimensional models based on the first Legendre coefficients are proven to be related to Padé approximations and are recognized to be more and more accurate as the dimension increases. Interestingly, this modeling allows computing in an accurate manner the root locus of time‐delay systems. Furthermore, as a by‐product of this result, taking into account the infinite‐dimensional remainders to keep track of the initial time‐delay system, stability criteria are proposed by analysis. Considering both infinite‐dimensional remainders as bounded delay‐free uncertainties, the small‐gain theorem provides a new sufficient condition of stability for retarded time‐delay systems, which can be implemented as a delay‐dependent frequency‐sweeping test. Our results are illustrated on several academic examples.

A case of infra-nodal Wenckebach conduction block with alternating bundle branch block

BackgroundAtrioventricular (AV) node normally has decremental conduction property and a longer refractory period than His-Purkinje system (HPS). This results in AV conduction delay or block at the level of AV node in response to short-coupled atrial premature beats. Prolonged refractoriness in HPS can produce unusual physiological patterns of AV conduction such as conduction delay or infra-nodal block in the distal elements of HPS.Case presentationWe present a case in which atrial premature stimulation produces infra-nodal Wenckebach conduction block which initiates long-short cycle sequence within the bundle branches resulted in alternating bundle branch block and atypical pattern of Ashman phenomenon.ConclusionsThis case highlights the importance of recognizing the unusual physiological AV conduction patterns of HPS. The long-short cycle sequence in the bundle branches of distal HPS and linking phenomenon can result in alternating bundle branch block without the presence of HPS disease.

Enhanced robust nanopositioning control for an X-Y piezoelectric stage with sensor delays: An infinite dimensional [formula omitted] optimization approach

In nanopositioning systems with capacitive displacement sensors, the analog-to-digital (A/D) conversion time is not negligible, particularly for the sub-nano resolution cases with 16 (or more) digital bits. The sensor induced delay will complicate modeling and control of such systems, due to the infinite dimensionality of the delay block. In this paper, we analyze the piezoelectric nanopositioner with a Hammerstein-like model incorporating uncertainties and a measurement delay. An infinite dimensional H∞ control approach is proposed for robust and nanopositioning control of the piezoelectric stage. To eliminate the fragility problem of the H∞ controller on its implementation, an equivalent structure including a Finite Impulse Response (FIR) filter is derived, and the matrix-function-based rational approximation (MFRA) for the FIR filter is presented. Real time experiments with the proposed control method are conducted where the positioning performance, robustness, and hysteresis compensation capability are comprehensively evaluated. Comparative studies demonstrate significant improvements over conventional methods such as Proportional–Integral–Derivative (PID) control and the finite dimensional robust control.

On Adaptive Moving Average Algorithms for the Application of the Conservative Power Theory in Systems with Variable Frequency

The Conservative Power Theory (CPT) emerged in recent decades as a theoretical framework for coping with harmonically distorted and unbalanced electric networks of ac power systems with a high participation of converter interfaced loads and generation. The CPT measurements are intrinsically linked to moving averages (MA) over one period of the grid. If the CPT is to be used in a low-inertia isolated-grid scenario, which is subjected to frequency variations, adaptive moving averages (AMA) are necessary. This paper reviews an efficient way of computing MAs and turns it into an adaptive one. It shows that an easily available variable time delay block, from MATLAB, causes steady-state errors in the measurements when the grid frequency varies. A new variable time delay block is, thus, proposed. Nonetheless, natural pulsations in the instantaneous power slip through MAs when the discrete moving average window does not fit perfectly the continuously varying period of the grid. A method consisting of weighing two MAs is reviewed and a new and effective hybrid AMA is proposed. The CPT transducers with the different choices of AMAs are compared via computer simulations of a single-phase voltage source feeding either a linear or a nonlinear load.

Data-Oriented View for Convolutional Coding With Adaptive Irregular Constellations

Current wireless systems offer various use-cases where conventional channel capacity focused performance criteria might not apply. Following the similar perspective, convolutional encoding can find more room due to its low complexity and low decoding delay. Besides, it has been also shown that error performance of a convolutional encoder can be improved further by using adaptive irregular constellations. A new performance measure, data-oriented approach, was recently proposed for the transmission of small data packets, i.e. mission-critical IoT applications, over fading channels. In this letter, delay performance gain resulting from convolution coding optimized irregular constellations is investigated. Then, we derive a new performance criterion based on delay and finite block length constraints. Based on this criterion, we design irregular constellations together with convolutional coding for short packet transmission.

Convergence and global stability analysis of fractional delay block boundary value methods for fractional differential equations with delay

In this paper, a new numerical scheme termed as fractional delay block boundary value methods (FDBBVMs) is proposed. It is an extended version of the block boundary value methods (BBVMs). The proposed scheme is used to find numerical solutions of the fractional delay differential equations including Caputo fractional derivative of βth order with 0<β<1 and a constant delay term. The estimation of the fractional-order derivative term is obtained by combining the mth-order Lagrange interpolating polynomial along with the pth-order BBVMs, and the constant delay term is dealt with certain modifications in the BBVM. Further, the convergence analysis of the proposed scheme is discussed and it is observed that the FDBBVM is convergent with order min{p,m−β+1}. Moreover, the scheme is shown to be globally stable and its computational efficiency and accuracy has been illustrated with the help of numerical examples.

Real-time measurements and performance analysis of closed-loop MIMO service for mobile operators

As fifth generation (5G) networks are starting to become commercial, user expectations in terms of new services become high as well. This signifies that mobile communications service providers need to build robust 5G new services as quickly and cost-efficiently as possible. Many new technologies rely on closed-loop (CL) and multiple input multiple output (MIMO) technologies due to emerging cooperation between nodes in next generation networks. In this paper, we first compare different multiantenna transmission modes namely: transmit diversity, open-loop (OL), and CL MIMO spatial multiplexing strategies to provide mobile network operator (MNO) services in terms of their characteristics, ,limitations and benefits. Later we investigate how launching a large-scale CL MIMO deployment strategy can affect the various key performance indicators (KPIs) of the existing services provided by Mobile Network Operators (MNOs) in real-operational network infrastructure in Turkey. Our practical experimental results indicate that, compared to OL MIMO system, CL MIMO can achieve large performance on a practical setup, where up to 3% improvement in cell average throughput, 9% in user throughput, 6% in spectrum efficiency, and 9% in channel quality indicator (CQI) and modulation coding scheme (MCS) are obtained, while reduction by 25% and 17% on sum delay and initial block error rates (IBLER) are observed.

On Hardware Implementation of Balanced S-boxes

An S-box is a non-linear transformation that takes n bits as input and returns m bits. This transformation is most easily represented as a nm lookup table. Most often, only balanced S-boxes are used in cryptography. This means that the number of input bits is equal to the number of output bits. The S-box is an important part of most symmetric ciphers. The selection of the correct substitution makes the link between the key and the ciphertext more complex (non-linear), which makes it much more difficult to hack. This paper deals with a hardware implementation of S-boxes. This implementation can be realized by using logical conjunction, disjunction, negation and delay blocks. The main indicator of productivity of such implementations is a circuit depth, namely the maximum length of a simple way of the circuit and a circuit complexity, namely the quantity of logic elements (negation elements are not taken into account). The article considers the standard synthesis methods (based on DNF, Shannon, Lupanov), proposes a new algorithm to minimize the complexity of an arbitrary Boolean functions system and a way to reduce the complexity of the circuit obtained after simplification by the ESPRESSO algorithm of DNF of the function related to the output of the S-box. To compare the efficiency of the methods, the C++ program was created that generates a circuit in the Verilog language. The estimates of depth and complexity are obtained for the schemes produced as a result of the programs operation. The article ends with a comparison of the efficiency of S-box schemes of known cryptographic standards obtained as the output of the program (with each other and with the result of the Logic Friday program).

Transesophageal echocardiographic predictors of intraventricular conduction delay in patients undergoing transcatheter aortic valve replacement

Introduction Patient anatomical features, such as shorter membranous septum (MS) length, on computed tomography have been shown to predict conduction abnormalities after transcatheter aortic valve replacement (TAVR). This relationship has not yet been evaluated using transesophageal echocardiography (TEE). Our hypothesis is that the distance from the aortic annulus to the septal bulge, a surrogate of MS distance and length, will be associated with a new interventricular conduction delay and heart block post-TAVR. Likewise, we hypothesize an implantation depth of the valve closer to the septal bulge will also predict post-TAVR interventricular conduction delay. Methods Comprehensive intraprocedural echocardiographic data were analyzed retrospectively on 88 patients who underwent TAVR under general anesthesia with TEE. Pre-procedural MS distance and post-procedural implantation depth (quantified as the inferior border of valve to septal bulge) were measured in the mid-esophageal long axis view of the aortic valve in mid-systole. EKGs were evaluated pre-TAVR and immediately post-valve deployment. Univariate logistic regression was used to identify predictors of a need for post-operative pacemaker (PM) implantation and new bundle branch block (BBB). Results The population consisted of 88 patients undergoing TAVR with TEE from 2017-2018 at our institution. The median age was 84, 45/88 (51.1%) were female. After TAVR, 7/88 (7.9%) had PPM placed and 21/88 (23.8%) had a new bundle branch block, transient or permanent. MS length was inversely associated with the risk of developing an interventricular conduction delay after TAVR (OR=0.19, CI 0.05-0.75, p=0.018). As shown in Table 1, the implantation distance was inversely associated with the need for a pacemaker or developing a new interventricular conduction delay after TAVR (OR=0.19, Cl 0.06-0.6, p=0.006). Discussion MS length and valve implantation depth on intraprocedural TEE are inversely associated with the risk of developing conduction abnormalities post-TAVR. TEE assessment may be comparable to CT in predicting post-TAVI high-grade atrioventricular block, and has the additional benefit of being performed intraprocedurally in selected patients.

P984Proof of endo-epicardial asynchrony of the left atrial wall in humans

Abstract Funding Acknowledgements Prof. Dr. NMS de Groot is supported by funding grants from CVON-AFFIP (914728), NWO-Vidi (91717339), Biosense Webster USA (ICD 783454) and Medical Del Introduction Treatment of atrial fibrillation (AF) is still suboptimal as mechanisms underlying AF initiation and persistence are incompletely understood. Endo-Epicardial asynchrony (EEA) plays an important role in AF persistence and has so far only been demonstrated in the right atrium (RA). Purpose To investigate whether EEA also exists in the thin walled left atrium (LA) and to measure the maximal degree of EEA between the endo- and epicardial layers during sinus rhythm (SR). Methods Simultaneous endo-epicardial mapping of the LA was performed during SR in 3 male patients (73 ± 1.5 years) with history of paroxysmal AF undergoing cardiac surgery including rhythm surgery and LA appendage amputation. Simultaneous endo-epicardial mapping was performed with a mapping clamp containing two electrode arrays of 8x16 electrodes (diameters: 0.4mm, interelectrode distance: 2mm) positioned exactly opposite to each other. The mapping clamp was introduced through the LA appendage with its tip towards the superior pulmonary vein. Local endo-epicardial activation time differences were determined by selecting the median time delay within the exact opposite electrode and its 8 surrounding electrodes. The asynchrony map consisted of the maximum of 2 medians from direct opposite electrodes. EEA was defined as time differences ≥15ms. Conduction delay (CD) and conduction block (CB) were defined as differences in local activation times between neighboring electrodes of respectively ≥7 and ≥12ms. Results A total of 35 SR beats were analyzed. Mean total activation time of the whole endo-epicardial LA tissue was 42.4 ± 9.5ms and did not differ between both layers (epicardium: 31.2 ± 9.9ms; endocardium: 37.8 ± 10.3ms; P= 0.62). CD and CB were observed in respectively 3.2% and 6.3% at the epicardium and 3.3% and 3.0% at the endocardium. The lowest amount of CD (5.2%) and CB (0.3%) was observed in the patient who had his first AF episode only 11 days prior to surgery. Also, no EEA was present in this patient. In two patients with paroxysmal AF &amp;gt;6 months, the prevalence of EEA was respectively 2.7% and 41.4% and the degree of EEA ranged from 15 to 44ms. Interestingly, the patient with the highest degree of EEA was diagnosed with paroxysmal AF for almost 5 years (Figure 1). Conclusion Our data provides evidence for the existence of EEA in the human left atrium which appears to be already present during SR. Knowledge of EEA and the ability to stage AF based on the degree of EEA is essential for individualized and staged future therapy for AF. Abstract Figure 1. The maximal degree of endo-epi

Design of efficient delay block for low frequency application

In recent years researchers have been focusing on the design of low power and small size oscillator for emerging areas of interest such as the internet of things (IoT) and biomedical applications. In this paper a new delay block for ring oscillator is proposed using CMOS inverter cascaded with inverted current starved inverter (CICSI). The designed delay block provides approximately 50% more delay with a smaller number of transistors than the conventionally designed circuits. Furthermore, a ring oscillator and a non-overlapping clock (NOC) generator are designed using it. The designed circuits can be used in switched capacitor (SC) circuits, analog mixed signal circuits to meet the need for low frequency portable biomedical applications. The designed circuits are simulated on Generic 90nm 1.2V Process Design Kit (GPDK90) using Cadence Virtuoso Design Environment. The simulation result shows the delay of the CICSI delay block is 592ps. The ring oscillator using 101 stages of delay block is designed and it is shown that it operates at a frequency of 17MHz with a power consumption of 420?W.

Some Insights on the Asymptotic Stabilization of a Class of SISO Marginally Stable Systems Using One Delay Block

In this paper, the stability of a class of marginally stable SISO systems is studied by applying a single one delay block as a feedback controller. More precisely, we consider an open-loop system with no zeros and whose poles are located exactly on the imaginary axis. Furthermore, a control law formed uniquely by a proportional gain and a delayed behavior is proposed for its closed-loop stabilization. The main ideas are based on a detailed analysis of the characteristic quasi-polynomial of the closed-loop system as the controller parameters (gain, delay) are varied. More precisely, by using the Mikhailov stability criterion, for a fixed delay value, we compute some gain margin guaranteeing the closed-loop stability. The particular case when the characteristic roots of the open-loop system are equidistantly distributed on the imaginary axis is also addressed. Finally, an illustrative example shows the effectiveness of the approach.

Virtual Engine In-Cylinder Pressure Sensor for Automobiles and Agricultural Tractors

The cylinder pressure signal is a very useful indicator for advanced high-performance internal-combustion engines equipped in modern automobiles and agricultural tractors. In this paper, a previous framework for the cylinder pressure estimation is conducted based on a transfer path model (between the cylinder pressure signal and the vibration signal) identified in frequency domain. The main idea behind the previous framework is based on the Kalman filter (of which the input is the engine structure vibration) for the augmented model formed by augmenting the cylinder pressure signal model with delay blocks and the transfer path model identified in time domain. Two combustion metrics, pressure peak Pmax and peak location Ploc, are used for evaluating the estimation framework under the transfer path identified in frequency domain. The estimation results are compared with both experimental data collected from a four-cylinder diesel engine and previous work results, and illustrate the effectiveness of the newly identified transfer path.

Exploring the Attack Surface of Blockchain: A Comprehensive Survey

In this paper, we systematically explore the attack surface of the Blockchain technology, with an emphasis on public Blockchains. Towards this goal, we attribute attack viability in the attack surface to 1) the Blockchain cryptographic constructs, 2) the distributed architecture of the systems using Blockchain, and 3) the Blockchain application context. To each of those contributing factors, we outline several attacks, including selfish mining, the 51% attack, DNS attacks, distributed denial-of-service (DDoS) attacks, consensus delay (due to selfish behavior or distributed denial-of-service attacks), Blockchain forks, orphaned and stale blocks, block ingestion, wallet thefts, smart contract attacks, and privacy attacks. We also explore the causal relationships between these attacks to demonstrate how various attack vectors are connected to one another. A secondary contribution of this work is outlining effective defense measures taken by the Blockchain technology or proposed by researchers to mitigate the effects of these attacks and patch associated vulnerabilities.

Time‐based all‐digital time‐to‐digital converter with pre‐skewed bi‐directional gated delay line time integrator

An all-digital first-order single-bit time-to-digital converter (TDC) with a pre-skewed bi-directional gated delay line (PS-BDGDL) time integrator with built-in self-quantisation is presented in this study. Pre-skewing is utilised to lower the per-stage delay of the BDGDL and minimise the skew errors of BDGDLs. The impact of the strength and timing of pre-skewed is analysed. The reduction of skew errors obtained from pre-skewing is also analysed. A design methodology combating the impact of process uncertainty on the TDC is developed. The TDC is designed in an IBM 130 nm 1.2 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM4 device models. Simulation results show that the impact of process spread on the performance of the TDC can be minimised by adjusting the delay of the key delay blocks and the per-stage delay of the gated delay stages. The figure-of-merit of the TDC outperforms reported TDCs alike.

A type of block withholding delay attack and the countermeasure based on type-2 fuzzy inference.

We proposed a new type of bitcoin withholding attack named block withholding delay (BWD). It is different from the traditional withholding attacks which always drop valid blocks. BWD attackers never discard blocks but they delay the submissions of blocks to the pool managers, resulting the pool failed in the mining competitions and loss of rewards. We analyzed the optimum strategy of a BWD attacker who split its computing power into two parts, one was utilized to launch BWD attacks on the victim pools, while the other part was used for solo mining. We present detailed quantitative analysis of the maximum incentive that an attacker can earn by carefully splitting its computing power, and demonstrated that the attacker can obtain higher incentives than its contribution to the network in different conditions. Furthermore, we proposed a countermeasure against BWD based on the interval type-2 Takagi-Sugeno-Kang fuzzy inference system (IT2-TSK-FIS). The principle is to modify the private payoff scheme of pools to increase the risk of losing revenues of the rogue miners who deliberately delay block submissions. The scheme dealing the uncertain cause of block delay using fuzzy inference, and it is so designed that it does not require modifications of public mining protocols or data structures of the bitcoin network, which makes it applicable in practical pools.

Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks

Invasive attacks, such as microprobing or focused-ion-beam (FIB) circuit editing are serious threats to security-related semiconductors. To ensure that there is security against invasive attacks, an effective countermeasure is to use a protective layer as a secure shield. Previous secure shield methods can be classified into one of two categories; detection circuits based on the delay difference or block ciphers. For the former, timing asymmetries caused by the capacitance of the probe are detected. The main drawback of this method is that it is highly vulnerable to chip editing by FIB equipment. FIB circuit editing can easily cripple the detection circuits of the secure shield. In contrast, the cryptographically secure shield based on the block cipher can provide strong protection against FIB circuit editing. However, it is prone to microprobing attacks because of its inability to detect the capacitance load of the probe. In this article, we propose a robust secure shield architecture against invasive attacks, including both probe attempts and the FIB circuit editing. The proposed method is based on the detection circuits with low hardware overhead and fast-analysis time and includes protection circuits to prevent information from being leaked.

Cardiac Resynchronization Defibrillator Therapy for Nonspecific Intraventricular Conduction Delay Versus Right Bundle Branch Block

BackgroundThe benefits of cardiac resynchronization therapy (CRT) in patients with non-left bundle branch block (LBBB) conduction abnormality have not been fully explored. ObjectivesThis study sought to evaluate clinical outcomes among Medicare-aged patients with nonspecific intraventricular conduction delay (NICD) versus right bundle branch block (RBBB) in patients eligible for implantation with a CRT with defibrillator (CRT-D). MethodsUsing the National Cardiovascular Data Registry implantable cardioverter-defibrillator (ICD) registry data between 2010 and 2013, the authors compared outcomes in CRT-eligible patients implanted with CRT-D versus ICD-only therapy among patients with NICD and RBBB. Also, among all CRT-D–implanted patients, the authors compared outcomes in those with NICD versus RBBB. Survival curves and multivariable adjusted hazard ratios (HRs) were used to assess outcomes including hospitalization and death. ResultsIn 11,505 non-LBBB CRT-eligible patients, after multivariable adjustment, among patients with RBBB, CRT-D was not associated with better outcomes, compared with ICD alone, regardless of QRS duration. Among patients with NICD and a QRS ≥150 ms, CRT-D was associated with decreased mortality at 3 years compared with ICD alone (HR: 0.602; 95% confidence interval [CI]: 0.416 to 0.871; p = 0.0071). Among 5,954 CRT-D–implanted patients, after multivariable adjustment NICD compared with RBBB was associated with lower mortality at 3 years in those with a QRS duration of ≥150 ms (HR: 0.757; 95% CI: 0.625 to 0.917; p = 0.0044). ConclusionsAmong non-LBBB CRT-D–eligible patients, CRT-D implantation was associated with better outcomes compared with ICD alone specifically in NICD patients with a QRS duration of ≥150 ms. Careful patient selection should be considered for CRT-D implantation in patients with non-LBBB conduction.

2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit

This study focuses on the design of a 2-1 switched-current (SI) multi-stage noise-shaping delta–sigma modulator with a digital noise-cancellation circuit. The noise-cancellation circuit is designed by employing various algorithms for designing the logic circuits and constructing a delay block with an inverter and a transmission gate. It can eliminate the higher-order quantisation noise from the first stage of the modulator completely. In the proposed differential current-mode sample-and-hold circuit, low-input impedance is presented with feedback and width-length adjustment in SI feedback memory cell, a coupled differential replicate with the common-mode feed-forward (CMFF) circuit is used to stabilise the common-mode bias voltage at input terminal, and a differential cross-connected CMFF circuit is utilised to fix the bias voltages. Post-layout simulations reveal that the simulated signal-to-noise-and-distortion ratio (SNDR) was 90.4 dB and the effective number of bit (ENOB) was 14.73 bits. Measurements show that the SNDR was 59.13 dB and the ENOB was 9.53 bits at a sampling rate of 10.24 MHz, an oversampling ratio of 256, and a signal bandwidth of 20 kHz. This design has a power requirement of 12.99 mW from a supply voltage of 1.8 V and occupies a core area of 0.14 mm2.