MOSFET Degradation Research Articles

Modeling and Analysis of Monitoring Gate-Oxide Degradation of SiC Power MOSFETs in Circuit by the Fingerprints of Voltage Switching Transient

Modeling and Analysis of Monitoring Gate-Oxide Degradation of SiC Power MOSFETs in Circuit by the Fingerprints of Voltage Switching Transient

Investigation on Gate Oxide Degradation of SiC MOSFET in Switching Operation

Investigation on Gate Oxide Degradation of SiC MOSFET in Switching Operation

Dynamic Degradation of Planar-Gate SiC MOSFETs After Total Ionizing Dose Radiation

Dynamic Degradation of Planar-Gate SiC MOSFETs After Total Ionizing Dose Radiation

Study on the relation between interface trap creation and MOSFET degradation under channel hot carrier stressing at cryogenic temperatures

In general, the degradation mechanism of MOSFETs has been discussed relating to hydrogen. For instance, interface traps are created due to the Si–H bond breakage at the MOS interface by hot (energetic) carriers under electrical stressing (e.g. channel hot carrier (CHC) and F-N stressing). In addition, it is also reported that hydrogen also relates to bulk trap creation. However, these hydrogen-related degradation mechanisms have been discussed based on the results within the conventional measurement temperature region. Recently, the reliabilities of MOSFETs at cryogenic temperatures have attracted much attention assuming that the electron devices are applied to quantum computing and space exploration. However, degradation mechanisms at cryogenic temperatures have yet to be fully clarified. In this paper, the degradations of MOSFETs under a CHC stressing in the temperature range of 77 K ∼ 300 K are investigated. Especially, we focus on the degradation of MOSFETs due to interface trap creation. As a result, MOSFETs degrade more under cryogenic temperature compared to that near RT. This result implies the existence of an additional degradation mechanism at cryogenic temperatures.

Parameter extraction using the transfer characteristics of vertically stacked Si nanosheet MOSFETs

We present a critical assessment and discussion of the presence of parasitic source-and-drain series resistance and normal electric field-dependent mobility degradation in undoped Si nanosheet MOSFETs. A simple explicit Lambert W function-based closed-form model, continuously valid from sub-threshold to strong conduction, was used to clearly describe the transfer characteristics. The model was applied to experimental vertically stacked GAA undoped Si nanosheet MOSFETs using phenomenon-related model parameter values extracted from measured data through suitable numerical optimization procedures. The conducted analysis reveals and explains how these two effects produce analogous deleterious consequences on these devices’ transfer characteristics.

Gate-Oxide Degradation Monitoring of SiC MOSFETs Based on Transfer Characteristic With Temperature Compensation

Gate-oxide degradation is a concern in SiC MOSFETs especially in safety critical applications such as aerospace and electric vehicles (EV). To address this concern, this paper presents an accurate gate-oxide degradation monitoring solution based on the SiC devices’ transfer characteristics. Specifically, a plug-in circuit for gate driver is proposed to extract the transconductance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> ) and threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V_th</i> ) values from transfer characteristic. By using the threshold voltage as gate-oxide aging reference and transconductance as the junction temperature reference, the two precursors are combined to obtain a temperature and package degradation independent estimate of the gate-oxide health. High-temperature gate bias (HTGB) and DC power cycling tests are used to confirm <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> ’s sensitivity to gate-oxide degradation and insensitivity to package degradation in kelvin-sourced discrete SiC MOSFETs. A simple circuit is proposed for on-board <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> measurement using the voltage drop on the common source inductance of the MOSFET. The measured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g_m</i> is converted into digital pulse width, which can be easily measured using a microcontroller. A comprehensive comparison is presented to demonstrate the merits of the proposed method. Lastly, the accuracy and sensitivity of temperature and aging measurements using the proposed method is validated experimentally.

An Investigation of Body Diode Reliability in Commercial 1.2 kV SiC Power MOSFETs with Planar and Trench Structures.

The body diode degradation in SiC power MOSFETs has been demonstrated to be caused by basal plane dislocation (BPD)-induced stacking faults (SFs) in the drift region. To enhance the reliability of the body diode, many process and structural improvements have been proposed to eliminate BPDs in the drift region, ensuring that commercial SiC wafers for 1.2 kV devices are of high quality. Thus, investigating the body diode reliability in commercial planar and trench SiC power MOSFETs made from SiC wafers with similar quality has attracted attention in the industry. In this work, current stress is applied on the body diodes of 1.2 kV commercial planar and trench SiC power MOSFETs under the off-state. The results show that the body diodes of planar and trench devices with a shallow P+ depth are highly reliable, while those of the trench devices with the deep P+ implantation exhibit significant degradation. In conclusion, the body diode degradation in trench devices is mainly influenced by P+ implantation-induced BPDs. Therefore, a trade-off design by controlling the implantation depth/dose and maximizing the device performance is crucial. Moreover, the deep JFET design is confirmed to further improve the body diode reliability in planar devices.

Investigation on Degradation of 1200-V Planar and Trench SiC MOSFET Under Surge Current Stress of Body Diode

Investigation on Degradation of 1200-V Planar and Trench SiC MOSFET Under Surge Current Stress of Body Diode

Operational Verification of Gate Drive Circuit With Condition Monitoring Function for Gate Oxide Degradation of SiC MOSFETs

Operational Verification of Gate Drive Circuit With Condition Monitoring Function for Gate Oxide Degradation of SiC MOSFETs

An Online Correction Method for Inaccuracy of Junction Temperature Monitoring Caused by Degradation of SiC MOSFETs

An Online Correction Method for Inaccuracy of Junction Temperature Monitoring Caused by Degradation of SiC MOSFETs

Ionization Radiation-Induced Reliability Degradation of SiC Power MOSFET

Ionization Radiation-Induced Reliability Degradation of SiC Power MOSFET

Investigation on temperature limitation and failure mechanism of SiC MOSFETs under avalanche conditions

To determine the latent degradation of SiC MOSFETs under single-pulse avalanche conditions, the stability of static characteristics and device capacitances is thoroughly studied by conducting Unclamped Inductive Switching (UIS) tests. No parametric shift is observed even though more than 90 % of the maximum avalanche energy is dissipated, indicating that devices fail in an abrupt mode. The avalanche failure turns out to be reaching the critical temperature. By introducing some corrections, including the temperature-dependent material properties, the aluminium layer, and the model of its melting process, the established model provides more accurate temperature results. The derived critical temperature is around 1200 K. All the devices suffer a fusion of metallization, which is considered to be the main mechanism of avalanche failure at the rated current region. With a sufficiently high current, the avalanche failure could also be accelerated by the turning-on of parasitic BJT.

Proton Irradiation-Induced Reliability Degradation of SiC Power MOSFET

The effect of 53 MeV proton irradiation on the reliability of silicon carbide power MOSFETs was investigated. Post-irradiation gate voltage stress was applied and early failures in time-dependent dielectric breakdown (TDDB) test were observed for irradiated devices. The applied drain voltage during irradiation affects the degradation probability observed by TDDB tests. Proton-induced single event burnouts (SEB) were observed for devices which were biased close to their maximum rated voltage. The secondary particle production as a result of primary proton interaction with the device material was simulated with the Geant4-based toolkit.

Oxide Electric Field-Induced Degradation of SiC MOSFET for Heavy-Ion Irradiation

This work presents an experimental study of heavy-ion irradiation with different particle linear energy transfer (LET), gate biases, and drain biases. The results reveal that when the irradiation biases are low, the SiC MOSFET does not experience single event effect (SEE) and the electrical properties remain unchanged (the devices are in the safe operating area (SOA)). However, the oxide breakdown voltage of the device is significantly decreased due to the latent damage generated by the irradiation. The experimental results, along with TCAD simulations, suggest that the latent damage induced by the irradiation in the gate oxide is closely related to the peak electric field in the gate oxide at the time of particle incidence. This peak electric field is determined by the potential difference between the two sides of the gate oxide, which is affected by the particle LET, gate biases, and drain biases together. The high potential is determined by the combined effect of the LET and the drain-source voltage. The impact ionization of the particle by the applied electric field causes the accumulation of holes in the JFET oxide, which leads to a decrease in the doping of the N− epitaxial layer and eventually causes a rise in the high potential near the JFET oxide. The low potential is determined by the gate bias, and the negative bias applied to the gate can further increase the potential difference between the two sides of the oxide, causing an increase in the peak electric field in the gate oxide and aggravating the gate oxide damage.

Real-Time Extraction of SiC mosfets’ Degradation Features Under Improved Accelerated Power Cycling Tests for DC-SSPC Application

The SiC MOSFET is a key component of the DC Solid-State Power Controller (DC-SSPC). The reliability of DC SSPCs can be improved by real-time online monitoring the degradation of SiC MOSFETs. At present, the degradation of SiC MOSFETs can be indirectly monitored using thermo-sensitive electrical parameters(TSEPs), however, their degradation can cause non-negligible measurement errors. Another limitation is that one type TSEPs can only reflect a certain form of degradation processs. Basis on this, in this paper, the real-time extraction method of SiC MOSFETs' degradation features under improved accelerated power cycling tests for DC SSPC application (i.e., average and standard deviation of on-resistance change rate ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avgk</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stdk</i> ) of the improved accelerated power cycling test) is proposed. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avgk</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stdk</i> can be easily obtained by simple calculations. This method can not only directly monitor the severe degradation of bonding wires, but also monitor the severe degradation of the solder layer without measuring the junction temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$T_{J}$</tex-math></inline-formula> ). Compared with the traditional solder layer degradation feature extraction method using thermal resistance which <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$T_{J}$</tex-math></inline-formula> is essential, the monitoring results using the proposed method are not affected by the degradation of TSEPs. Finally, the effectiveness of the proposed method is verified by experiment results.

Investigation of Off-State Stress Induced Degradation of SiC MOSFETs Under Short-Circuit Condition

Investigation of SiC MOSFETs short-circuit (SC) degradation mechanism is critical to improve the overall reliability of power converters. At present, research on the SiC MOSFETs degradation mechanism mainly focuses on the on-state phase of the SC period. While, ruggedness of SiC MOSFETs in the off-state phase of short-circuit tests (SCTs) were neglected. In this paper, SiC MOSFETs degradation mechanism in the off-state phase of SCTs are investigated comprehensively. Specifically, distribution and magnitude of electrothermal stress of devices under test (DUTs) in the off-state phase of SCTs are analyzed by TCAD simulation. Which reveals two important phenomena: i) the device will suffer from long-term high temperature and high electric field stress in the off-state phase when negative turn-off gate voltage (Vgs-off) is applied; ii) high hole current in the channel region will last for several microseconds after the device is turned off. The observed SiC MOSFETs degradation in the off-state phase of SCTs is then proved by experiments, through which, the excessively low Vgs-off can reduce the SC capability of SiC MOSFETs is concluded. Moreover, the degradation results of static parameters of SiC MOSFETs are presented and the degradation mechanism is analyzed in detail.

Investigation on safe-operating-area degradation and failure modes of SiC MOSFETs under repetitive short-circuit conditions

• Repetitive short circuits cause thermal runaway failure of SiC MOSFETs • Safe operating area reduces after repetitive short-circuit conditions • Repetition frequency and duration affect degradation of SiC MOSFETs • Hole traps in gate oxides induce degradation of SiC MOSFETs The safe operating area is an operating area with high reliability for SiC MOSFET, and its degradation may cause power electronic system failure. The safe-operating-area degradation and the failure modes of 1200V/66A SiC MOSFET caused by repetitive short-circuit stress with different short-circuit times and short-circuit time intervals are investigated. A short circuit test platform with circuit protection is configured to degrade DUT(device under test), and the safe operating area is characterized after repetitive short circuit stress is applied. The degradation mechanism of the safe operating area is explained by the 1-D electro-thermal coupling model based on Sentaurus TCAD. When the critical short-circuit duration is 12μs, the single short-circuit failure mode of DUT with 400V dc-bus voltage is a gate-source short-circuit failure. From the short circuit test result, the failure modes under repetitive short-circuit conditions include gate-source short-circuit failure and thermal runaway, depending on the repetitive short-circuit time intervals. For the same short-circuit time interval, when the short-circuit duration is 10μs, the weakest boundary of the safe operating area is the blocking voltage. When the short-circuit duration is 2μs, all three boundaries of the safe operating area are contracted. These results are confined to 400V dc-bus voltage, 25°C case temperature, and 18V/-3V gate-source voltage. Schematic diagram of the degradation of the safe operating area of the device under long-term operating conditions. (a) Small margin, failure (b) Large margin, high cost (c) Optimal design

Proton induced radiation effect of SiC MOSFET under different bias

Radiation effects of silicon carbide metal–oxide–semiconductor field-effect transistors (SiC MOSFETs) induced by 20 MeV proton under drain bias (V D = 800 V, V G = 0 V), gate bias (V D = 0 V, V G = 10 V), turn-on bias (V D = 0.5 V, V G = 4 V) and static bias (V D = 0 V, V G = 0 V) are investigated. The drain current of SiC MOSFET under turn-on bias increases linearly with the increase of proton fluence during the proton irradiation. When the cumulative proton fluence reaches 2 × 1011 p⋅cm−2, the threshold voltage of SiC MOSFETs with four bias conditions shifts to the left, and the degradation of electrical characteristics of SiC MOSFETs with gate bias is the most serious. In the deep level transient spectrum test, it is found that the defect energy level of SiC MOSFET is mainly the ON2 (E c – 1.1 eV) defect center, and the defect concentration and defect capture cross section of SiC MOSFET with proton radiation under gate bias increase most. By comparing the degradation of SiC MOSFET under proton cumulative irradiation, equivalent 1 MeV neutron irradiation and gamma irradiation, and combining with the defect change of SiC MOSFET under gamma irradiation and the non-ionizing energy loss induced by equivalent 1 MeV neutron in SiC MOSFET, the degradation of SiC MOSFET induced by proton is mainly caused by ionizing radiation damage. The results of TCAD analysis show that the ionizing radiation damage of SiC MOSFET is affected by the intensity and direction of the electric field in the oxide layer and epitaxial layer.

Avalanche capability degradation of the parallel-connected SiC MOSFETs

Silicon carbide (SiC) MOSFET chips are often connected in parallel in a module to increase the current rating. However, the current capability is degraded due to unbalanced current and temperature distributions which affect the avalanche processes particularly in extreme operating conditions. To obtain the root cause of the degradation and identify the dominant factors, single-pulse avalanche testing is carried out in this study, and TCAD simulation is used for mechanism analysis. It is revealed that electrothermal parameters have different effects on current sharing in different stages of avalanching. The corresponding failure mechanisms are analyzed, and the main cause of avalanche failure with parallel devices is found to be the difference in breakdown voltage. Device with smaller BV shares more current as well as more heat, which fails first eventually. To resolve such issues, proper device screening/paring should be carried out. The findings are helpful for a better understanding of avalanche capability degradation in parallel devices application.

Comprehensive Study of MOSFET Degradation in Power Converters and Prognostic Failure Detection Using Physical Model

Comprehensive Study of MOSFET Degradation in Power Converters and Prognostic Failure Detection Using Physical Model