Semiconductor Wafer Defect Research Articles

Semiconductor Wafer Defect Detection Based on Machine Learning

Semiconductor wafers are widely used in integrated circuit chips. Because of the complex production process, it is easy to cause various defects. Therefore, the defect detection of semiconductor wafers is an important means to ensure their yield and productivity. This paper mainly expounds on the detection method of wafer defects combined with the machine vision algorithm, including the CNN model, and the classification of the learning-based methods. Current problems and future prospects for total crystalline circle defect detection are discussed in the end.

Low complex CNN for semiconductor wafer defect detection

Fabrication of semiconductor wafers is a complex process and chances of defect wafers are high. Because of defective wafers the circuit patterns will not be created correctly and it is necessary to identify them. Manual identification of defects are time consuming and expensive. Deep learning methods are widely used for defect detection. In this paper we propose a simple Convolutional Neural Network (CNN) model for classification of nine defects in wafers. A custom CNN consisting of 9 layers is used for the classification of defects as Center, Donut, Edge-Loc, Edge-Ring, Loc, Random, Scratch, Near-full, and None. Performance of the model is evaluated using WM-811K dataset. Results shows that the model classifies the defects with high confidence score and an accuracy of 99.1% is achieved using this method. Further, the convolution operation in the CNN is realized using Coordinate Rotation Digital Computer (CORDIC) algorithm. The model is implemented in Field Programmable Gate Arrays (FPGA) and proved less complex method and consume less computational power than conventional methods.

Development of High-Resolution Nuclear Emulsion Plates for Synchrotron X-Ray Topography Observation of Large-Size Semiconductor Wafers

Characterization of defects in semiconductor wafers is essential for the development and improvement of semiconductor devices, especially power devices. X-ray topography (XRT) using synchrotron radiation is a powerful methods used for defect characterization. To achieve detailed characterization of large-size semiconductor wafers by synchrotron XRT, we have developed nuclear emulsion plates reaching a high-resolution and wide dynamic range. We have shown that higher-resolution XRT images could be obtained using emulsions with smaller iodobromide crystals, and demonstrated clear observation of threading edge dislocations in a SiC epitaxial layer having small contrast. Furthermore, we demonstrated XRT image acquisition for almost all of a 150-mm SiC wafer with one plate. Our development will contribute to advances in electronic materials, especially in the field of power electronics, in which defect characterization is important for improving the performance and yield of devices.

A deep residual neural network for semiconductor defect classification in imbalanced scanning electron microscope datasets

The detection of defects using inspection systems is common in a wide range of corporations such as semiconductor industries. The use of techniques based on deep learning (DL) and, in particular, convolutional neural networks (CNNs), emerges as a powerful tool to classify aesthetic defects and other unwanted anomalies in industrial automation applications marked by their natural complexity and high degree of variability. In this paper, an effective hybrid deep residual neural network approach is presented which merges traditional computer vision techniques to perform an appropriate defect segmentation and a deep residual neural network-grid search-based hyperparameter optimization for defect classification. The proposed model has been compared with other baseline algorithms and with other hybrid methods-based CNNs using different performance metrics such as F1-score, Cohen’s kappa coefficient, confusion matrix and computing time, on imbalanced datasets obtained from scanning electron microscope (SEM) images. The results obtained illustrate that the designed hybrid method provides the best defect classification of defects in semiconductor wafers in terms of F1-score (99.443%) while consuming the least computational time.

A novel hybrid resampling for semiconductor wafer defect bin classification

AbstractGenerally, defective dies on semiconductor wafer maps tend to form spatial clusters in distinguishable patterns which contain crucial information on specific problems of equipment or process, thus it is highly important to identify and classify diverse defect patterns accurately. However, in practice, there exists a serious class imbalance problem, that is, the number of the defective dies on semiconductor wafer maps is usually much smaller than that of the non‐defective dies. In various machine learning applications, a typical classification algorithm is, however, developed under the assumption that the number of instances for each class is nearly balanced. If the conventional classification algorithm is applied to a class imbalanced dataset, it may lead to incorrect classification results and degrade the reliability of the classification algorithm. In this research, we consider the semiconductor wafer defect bin data combined with wafer warpage information and propose a new hybrid resampling algorithm to improve performance of classifiers. From the experimental analysis, we show that the proposed algorithm provides better classification performance compared to other data preprocessing methods regardless of classification models.

A voting-based ensemble feature network for semiconductor wafer defect classification

Semiconductor wafer defects severely affect product development. In order to reduce the occurrence of defects, it is necessary to identify why they occur, and it can be inferred by analyzing the patterns of defects. Automatic defect classification (ADC) is used to analyze large amounts of samples. ADC can reduce human resource requirements for defect inspection and improve inspection quality. Although several ADC systems have been developed to identify and classify wafer surfaces, the conventional ML-based ADC methods use numerous image recognition features for defect classification and tend to be costly, inefficient, and time-consuming. Here, an ADC technique based on a deep ensemble feature framework (DEFF) is proposed that classifies different kinds of wafer surface damage automatically. DEFF has an ensemble feature network and the final decision network layer. The feature network learns features using multiple pre-trained convolutional neural network (CNN) models representing wafer defects and the ensemble features are computed by concatenating these features. The decision network layer decides the classification labels using the ensemble features. The classification performance is further enhanced by using a voting-based ensemble learning strategy in combination with the deep ensemble features. We show the efficacy of the proposed strategy using the real-world data from SK Hynix.

Defect classification on semiconductor wafers using Fisher vector and visual vocabularies coding

The main trend in the classification of defects in semiconductor wafers from scanning electron microscopy images is the use of convolutional neural networks. These methods allow automatic feature extraction and supply high accuracy. However, they have limitations since they need a large number of samples in the training phase and are computationally expensive in general. Methods based on visual vocabularies are an efficient alternative to this type of networks that can be implemented with a reduced number of training samples. Although visual vocabularies have been successfully used in different image classification problems, to our knowledge they have never been tested in the classification of defects in semiconductor material wafers from scanning electron microscopy images. On the rectangular region holding the defect, the scale-invariant feature transform algorithm is applied to determine the points of interest and to calculate the descriptors of the patches containing these points. By training a clustering algorithm with these features, a visual vocabulary is created to describe each image as a bag of visual words. Two approaches for coding the descriptors are studied: (i) The more traditional one performs a count of the occurrence of each visual word, and (ii) a modern approach known as Fisher vector which measures the deviation between each descriptor and the generative Gaussian mixture model. Comparing both variants using support vector machines it is seen that Fisher vector coding is computationally more efficient and reports better classification results. The usefulness of visual vocabularies for defect classification on semiconductor wafers is showed by the 91.89% and 93.13% accuracy obtained for bag of visual words and Fisher vector coding, respectively. The training and testing times are lower than 5 min for both approaches.

Semiconductor wafer defect classification using convolution neural network: a binary case

With the multitude of steps used in semiconductor industry, automation is being practiced extensively in its manufacturing processes to guarantee quality of manufactured chips and improvement in production. At front end of line, wafer are probed and defective chips are segregated. From this data wafer bin map are generated, these show defects on the surface of wafers. If analysis of wafer bin map is done manually, this may result in incorrect categorization of defects due to human error and lack of judgement. Thus, the rationale behind this research study is to determine the scope of vision-based methods for automatic classification of wafer defects. In view of this, a classifier which detects Type A and Type B defects in wafers is proposed. It involves a Convolution Neural Network (CNN) based binary classifier. 250 Images of each class of wafer bin map dataset, is used to conduct the study on five layer CNN architecture. The proposed setup gives the test accuracy of 97.7%.

A Novel Method Based on Deep Convolutional Neural Networks for Wafer Semiconductor Surface Defect Inspection

Semiconductor wafer is widely used in welding robot, spray robot, unmanned material delivery vehicle, and detection station sensor. The defects of semiconductor wafer, such as stains, burrs, scratches, and holes generated in the manufacturing process, severely affect the quality of downstream products. Therefore, the inspection of wafer defect could not be neglected. Traditional semiconductor wafer defect inspection methods based on handcrafted features heavily rely on the expertise and are limited in some application scenario. In this article, a novel method based on deep convolutional neural networks for semiconductor wafer surface defect inspection is proposed. First, a new structure of feature pyramid networks with atrous convolution (FPNAC) is developed to extract the features and to generate feature maps. Second, the feature maps are fed into region proposal network (RPN) to generate region proposals. Finally, the region proposals are aligned to corresponding size as the inputs of deep multibranches neural network (DMBNN) consisting of three branches, to classify and segment the defects precisely. Experimental results demonstrate that the proposed method yields good comprehensive performance with mean pixel accuracy (MPA) 93.97% and mean intersection over union (MIoU) 83.58%.

Wafer defect detection by a polarization-insensitive external differential interference contrast module.

We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

Semiconductor Wafer Defect Classification Using Support Vector Machine with Weighted Dynamic Time Warping Kernel Function

Semiconductor Wafer Defect Classification Using Support Vector Machine with Weighted Dynamic Time Warping Kernel Function

Tolerance limits under Poisson regression based on small-sample asymptotic methodology

ABSTRACTThis article explores the calculation of tolerance limits for the Poisson regression model based on the profile likelihood methodology and small-sample asymptotic corrections to improve the coverage probability performance. The data consist of n counts, where the mean or expected rate depends upon covariates via the log regression function. This article evaluated upper tolerance limits as a function of covariates. The upper tolerance limits are obtained from upper confidence limits of the mean. To compute upper confidence limits the following methodologies were considered: likelihood based asymptotic methods, small-sample asymptotic methods to improve the likelihood based methodology, and the delta method. Two applications are discussed: one application relating to defects in semiconductor wafers due to plasma etching and the other examining the number of surface faults in upper seams of coal mines. All three methodologies are illustrated for the two applications.

Diffraction phase microscopy: monitoring nanoscale dynamics in materials science [invited

Quantitative phase imaging (QPI) utilizes the fact that the phase of an imaging field is much more sensitive than its amplitude. As fields from the source interact with the specimen, local variations in the phase front are produced, which provide structural information about the sample and can be used to reconstruct its topography with nanometer accuracy. QPI techniques do not require staining or coating of the specimen and are therefore nondestructive. Diffraction phase microscopy (DPM) combines many of the best attributes of current QPI methods; its compact configuration uses a common-path off-axis geometry which realizes the benefits of both low noise and single-shot imaging. This unique collection of features enables the DPM system to monitor, at the nanoscale, a wide variety of phenomena in their natural environments. Over the past decade, QPI techniques have become ubiquitous in biological studies and a recent effort has been made to extend QPI to materials science applications. We briefly review several recent studies which include real-time monitoring of wet etching, photochemical etching, surface wetting and evaporation, dissolution of biodegradable electronic materials, and the expansion and deformation of thin-films. We also discuss recent advances in semiconductor wafer defect detection using QPI.

Diffraction phase microscopy: principles and applications in materials and life sciences

The main obstacle in retrieving quantitative phase with high sensitivity is posed by the phase noise due to mechanical vibrations and air fluctuations that typically affect any interferometric system. In this paper, we review diffraction phase microscopy (DPM), which is a common-path quantitative phase imaging (QPI) method that significantly alleviates the noise problem. DPM utilizes a compact Mach–Zehnder interferometer to combine several attributes of current QPI methods. This compact configuration inherently cancels out most mechanisms responsible for noise and is single-shot, meaning that the acquisition speed is limited only by the speed of the camera employed. This technique is also nondestructive and does not require staining or coating of the specimen. This unique collection of features enables the DPM system to accurately monitor the dynamics of various nanoscale phenomena in a wide variety of environments. The DPM system can operate in both transmission and reflection modes in order to accommodate both transparent and opaque samples, respectively. Thus, current applications of DPM include measuring the dynamics of biological samples, semiconductor wet etching and photochemical etching processes, surface wetting and evaporation of water droplets, self-assembly of nanotubes, expansion and deformation of materials, and semiconductor wafer defect detection. Finally, DPM with white light averages out much of the speckle background and also offers potential for spectroscopic measurements.

Structural Defect Studies of Semiconductor Crystals with Laue Topography

A defocused Laue diffractometer setup operating with the white beam of a high energy X-ray tube has been used for a topographic visualization of structural defects in semiconductor wafers. The laboratory white beam X-ray topograph of a Czochralski Si wafer with oxygen precipitates grown in an annealing process is compared to a μPCD image. Further, the dislocation network in a VGF GaAs wafer is studied under thermal annealing up to 1140°C and the in-situ capability of the setup is demonstrated.

An unsupervised neural network approach for automatic semiconductor wafer defect inspection

Semiconductor wafer defect inspection is an important process before die packaging. The defective regions are usually identified through visual judgment with the aid of a scanning electron microscope. Dozens of people visually check wafers and hand-mark their defective regions. Consequently, potential misjudgment may be introduced due to human fatigue. In addition, the process can incur significant personnel costs. Prior work has proposed automated visual wafer defect inspection that is based on supervised neural networks. Since it requires learned patterns specific to each application, its disadvantage is the lack of product flexibility. Self-organizing neural networks (SONNs) have been proven to have the capabilities of unsupervised auto-clustering. In this paper, an automatic wafer inspection system based on a self-organizing neural network is proposed. Based on real-world data, experimental results show, with good performance, that the proposed method successfully identifies the defective regions on wafers.

Topography of Defect Parameters on Si and GaAs Wafers

A new measurement technique is presented which is able to analyse defects in semiconductor wafers with pieces of information like DLTS. However, in contrast to DLTS the technique is non-destructive, contact- free and highly spatially resolving. Shallow and deep levels can be investigated in un-doped or doped semiconductors. In addition, photoconductivity and carrier lifetime topograms of wafers are possible with extremely low injection levels.

Quantitative defect studies in semiconductor TEM samples prepared by low angle ion milling

Due to the wealth of information, both analytical and structural that can be obtained from it TEM always has been a favorite tool for the analysis of process-induced defects in semiconductor wafers. The only major disadvantage has always been, that the volume under study in the TEM is relatively small, making it difficult to locate low density defects, and sample preparation is a somewhat lengthy procedure. This problem has been somewhat alleviated by the availability of efficient low angle milling.Using a PIPS® variable angle ion -mill, manufactured by Gatan, we have been consistently obtaining planar specimens with a high quality thin area in excess of 5 × 104 μm2 in about half an hour (milling time), which has made it possible to locate defects at lower densities, or, for defects of relatively high density, obtain information which is statistically more significant (table 1).

Non-Contact, Wafer-Scale Deep Level Transient Spectroscopy (DLTS) Based on Surface Photovoltage (SPV)

ABSTRACTWe present a new version of a deep level transient spectroscopy which is suitable for non-contact, non-destructive determination of deep level defects in semiconductor wafers without preparation of metal-semiconductor diodes or p-n junctions.The method relies on deep level thermal emission measurements by the surface photovoltage (SPV) transient following an optical filling pulse. Non-equilibrium occupation of deep levels is realized within the native surface depletion region by the capture of excess minority carriers. Since the native Schottky-type surface barrier is commonly present on semiconductor surfaces, the approach requires no wafer pre-treatments. Non-contact SPV measurements are realized using a capacitive coupling to the wafer front and the wafer back.The quantitative principles of the SPV-DLTS approach are discussed using experimental data obtained on GaAs.

Method for determining structural defects in semiconductor wafers by ultrasonic microscopy : General Electric Company U.S. Patent No. 4,741,212 (3 May 1988)

Method for determining structural defects in semiconductor wafers by ultrasonic microscopy : General Electric Company U.S. Patent No. 4,741,212 (3 May 1988)