Defect Inspection Tools Research Articles

Basal Plane Dislocation Slip Band Characterization and Epitaxial Propagation in 4H SiC

Correlation of X-ray topography and production line defect inspection tools has demonstrated the capability of in-line tools to differentiate between geometrically comparable basal plane slip bands (BPSB) and bar stacking faults (BSF) on 4H SiC wafers. BPSBs were found to propagate through epitaxial growth at high rates and with similar photoluminescence signatures to post-epitaxy BSFs. Molten KOH etching post-epitaxy provided evidence of distinguishing features between BPSBs and BSFs, suggesting that the defects were indeed correctly identified by in-line defect inspection tools pre-epitaxy.

Single-Wafer Chemical Mechanical Planarization (CMP) on 150mm Silicon Carbide Substrate with Superior Surface Finish and Removal Efficiency

Silicon carbide (SiC) has excellent performances such as superior thermal conductivity, good carrier mobility and high chemical stability in comparison with those of silicon (Si). SiC has a great potential in the area of the next generation power controlling devices, high performance communication, and LED lighting. Chemical mechanical polishing (CMP) techniques combine mechanical polishing with a chemical etching action and can achieve truly defect-free surface with wafer flatness control capability, which is important for obtaining good epitaxial layer. However, Silicon carbide (SiC) presents many challenges for wafer surface treatment because of its high hardness and remarkable chemical inertness. Currently, low material removal rate (MRR) of CMP technique is a fundamental limit, it extends the CMP process time and effects the yield in mass production of substrate.In this study, we proposed an ultra-high MRR CMP process on 150mm n-doped, 4° off-axis, single crystal, 4H-SiC wafers. The process was developed at Applied Materials Mirra Durum® CMP configured with the membrane polishing head using an acidic slurry with strong potassium permanganate oxidant and thermoplastic polyurethane (TPU) pad. The effect of polishing process parameters (speed of the head and platen rotating, head sweeping distance and applied pressure) on MRR are analyzed in JMP® (SAS institute) while a design of experiments (DOE) is employed. The chemical composition of slurry, which is also critical to MRR, has also been evaluated via DOE. Potassium permanganate with certain concentration has been selected as oxidant and aluminum oxide micron particle has been used as abrasive. We have also conduct studies on the SiC wafer flatness control, which is proven to depend on structural design of polishing head. The head has been optimized to offer a flexible zone pressure control, therefore the impact on wafer flatness during the CMP process has also been minimized. In addition, accepted industry measurements of surface roughness, surface defect and wafer deformation are also taken into consideration.The successful development of CMP process provided an optimized MRR result, the reported MRR is 22.5 um/hr from C face and 6.4um/hr from Si face. The MRR have achieved highest level within literature and industry. The MRR results are analyzed by least–square modelling, which reveals that Prob >|t| is less than 0.05 for platen rotation speed and membrane pressure. Prediction profile demonstrates that MRR typically follows Preston’s law, which is a linear function of the platen speed and the pneumatic pressure applied to substrate. MRR is highly stable throughout a 2000-wafer repeat run with wafer-to-wafer uniformity of 2.4-3.7%. Scratch-free wafer surfaces are observed for the ultra-smooth wafers via atomic force microscopy (AFM) and defect inspection (Candela) tool. Roughness on Si face has been reduced from 2.0-2.5nm to less than 0.15nm with acceptable repeatability. Surface defects including scratches, pits have been greatly reduced. Total scratch length of 10mm has been achieved. Total thickness variation (TTV) is measured to characterize wafer flatness by Tropel tool, which indicates that the total amount of removed thickness on faces has a profound influence on TTV. With focused process control, post-CMP TTV can be improved by 0.6 ~2.1 um from pre-CMP TTV.

Experimental and Modelling Investigation of Re-Adhesion Mechanism of Detached Nanoparticles to Wafer Surface in Spin Rinse Process

Adhesive particles on polished wafers are detached by e.g. scrubbing, and removed by liquid flow from the wafer. However, the relationship between the characteristic of liquid flow and the removal of detached particles has not yet been examined in detail. Therefore, the re-adhesion of detached particles to wafer surfaces in liquid flow on rotating wafers was experimentally investigated. The number of residue particles on a wafer was counted using a defect inspection tool after de-ionized water (DIW) rinse for particle removal. To discuss the mechanism of particle removal, a model was constructed and compared with experimental results. The model is based on boundary layer theory of fluid dynamics and advection diffusion theory of transport phenomena for particle removal in liquid flow near the wafer surface. The model results confirmed that detached particles in liquid flow moved into the sublayer and re-adhered to the wafer surface by diffusion. Moreover, particles in the sublayer, where the liquid velocity is several hundred um/s, could not be moved from the sublayer and removed from the wafer. It was also found that the number of particles re-adhering to the wafer surface depends on the Sherwood number.

Table-Top Evaluation Approach to Design Post-CMP Clean Chemicals

In todays advanced integration technology, there have been tough requirements for CMP process, particularly for post CMP clean because even minute defects heavily impact on device yield. CMP slurries have small abrasive particles and many additives, which remain on post CMP wafer and cause various types of defect. However, strong bulk chemical cleaners can easily damage a polished surface of wafer. Thus how to strike right balance between high cleanability and low erodibility is major challenge for post CMP clean chemical development. Another large difficulty to develop pCMP clean chemicals is that using full wafer-scale CMP and defect inspection tools takes too much time and cost. As a pCMP clean chemicals manufacturer, we have been trying to introduce a small coupon-scale evaluation metrology so that we can conduct screening tests for many candidate chemicals and their combinations in a quick and least cost manner. This metrology includes electrochemical analysis, surface analysis and also benchmarking test using a table-top polisher and a lab-size cleaning unit. In this paper, we will report how we can apply this coupon-scale evaluation metrology to post CMP clean evaluation for contact plugs. In CMP process involving contact plugs between transistor and M1, great care is necessary because the finest patterns are formed in this region. Typically, tungsten (W) is employed for plug metal and acidic chemicals have been used for post CMP clean because of its strong removability of iron (Fe) that is contained in slurries as a catalyst for W film oxidation. However acidic chemicals often do not have adequate particle removability. Therefore it is one of the top issues to make Fe removability and particle removability compatible. And also it is desirable that we can rapidly evaluate Fe and particle removability in small lab-scale. One of approach we would like to present is evaluation approach to Fe removability. Fe can be quantified by TXRF or VPD-ICP-MS after wafer polish and clean with CMP tools. But it is not practical to use every time these methods in initial screening stage due to their cost. For this purpose, we have applied electrochemical measurement approaches such as Tafel-plot and OCP (Open Circuit Potential) to estimate Fe removability for various chemicals. Tafel plot measurement provides corrosion current (Ecorr). A cleaner that has higher Fe removability shows higher corrosion current because the cleaner solution dissolves passivation film like a Fe2O3. So this method can compare Fe removal efficiency between cleaners. Open Circuit Potential (OCP) reflects surface passivation film condition. When passivation film is formed on surface, OCP rises because oxidation current becomes small. In contrast, when passivation film is removed, OCP drops. Therefore Fe removal speed can be compared by measuring time-dependent OCP for iron electrode with passivation layer in cleaner solution. In this presentation we will review details of metrology and also comparison of results between coupon-size, lab-level screenings and wafer size tests. Figure 1

Incoming and Inline Defectivity Control Solutions for Silicon Carbide Manufacturing

Si l icon car b ide (Si C ) man u f act u ring is transitioning from 4 inch wafers to 6 inch wafers for production line devices. The main obstacle for SiC manufacturing high yield is defect control. Defectiveness inline control is well established for silicon power device. However, there are two main challenges related to SiC technology. The first challenge is incoming 4H-SiC substrates defectivity and epi layer crystallographic defects. The second challenge is inline defect detection at process steps such as implantation and annealing activation [,]. Defect detection and classification are difficult with current defect inspection tools because of substrate transparency at visible light, color variation, roughness, and wafers’ high warpage. In addition, SiC device integration has been requesting specific optimization. In this paper, collaboration studies have been done to develop solutions to these challenges. Yield correlation analyses have validated the process control flow set to address these two major challenges and to enable the fast ramp of the 6” production line of SiC devices.

Image Simulation and Analysis to Predict the Sensitivity Performance of a Multi-Electron Beam Wafer Defect Inspection Tool

Image Simulation and Analysis to Predict the Sensitivity Performance of a Multi-Electron Beam Wafer Defect Inspection Tool

Patterning of defect arrays with e-beam lithography used to develop a high throughput e-beam defect inspection tool

SUNY Poly SEMATECH has established an infrastructure development program to ensure that needed beam based metrology tools and techniques are available for leading edge semiconductor processes and devices. The design, development, and fabrication of high quality dense array samples with ≤16 nm defects at known locations is a key requirement to assessing new inspection technologies. Due to the technical difficulties of creating high quality programmed defect samples at the required sizes, the authors have undertaken multiple paths of electron beam lithographic development, supporting organizations and processing techniques to optimize and deliver the needed samples. In doing so, this program has created a snapshot of electron beam lithographic capability. This paper discusses our experience with electron beam lithography used to create the arrays samples.

Variation in phase defect size on extreme ultraviolet mask before and after reflective multilayer coating

It is very difficult to predict how multilayer defects known as “phase defects” impact on wafer printed image when embedded in an extreme ultraviolet (EUV) mask. Therefore, researchers have reported many techniques to analyze and characterize phase defects using scanning probe microscopes (SPMs) and phase defect inspection tools that employ deep ultraviolet or EUV optics. To characterize the phase defects using SPM or other inspection tools, preparing and employing a programmed phase defect mask is a practical way to address the task because the locations, sizes, and quantity of phase defects can be defined to fit experiments. For this study, a programmed phase defect mask was prepared to investigate the size uniformity of the programmed phase defects. The designed phase defects were holes 40-, 50-, 70-, or 80-nm-wide and 4.5-nm-deep. Using a SPM, the phase defects were measured for their depths and widths before and after coating with the multilayer. As a result, variations in the measured depths and widths were much smaller than the defect-to-defect variations, reflecting measurement repeatability. In addition, the variations in the depths and widths of the phase defects after multilayer coating were larger than before coating. It was also found that a given group of phase defects exhibited significant variations in depth and width after multilayer coating, even if they were the same prior to coating. This result indicated that it is difficult to estimate precoating phase defect sizes based on measurements after the multilayer is coated.

Development of element technologies for EUVL

Abstract Thirty years have passed since the first report on extreme ultraviolet lithography (EUVL) was presented at the annual meeting of the Japanese Society of Applied Physics in 1986. This technology is now in the manufacturing development stage. The high-volume manufacturing of dynamic-random-access-memory (DRAM) chips with a line width of 15 nm is expected in 2016. However, there are critical development issues that remain: generating a stand-alone EUV source with a higher power and producing a mask inspection tool for obtaining zero-defect masks. The Center for EUVL at the University of Hyogo was established in 2010. At present, it utilizes various types of equipment, such as an EUV mask defect inspection tool, an interference-lithography system, a device for measuring the thickness of carbon contamination film deposited by resist outgassing, and reflectivity measurement systems.

Phase defect detection signal analysis: dependence of defect size variation

The influence of the size or volume of the phase defect embedded in the extreme ultraviolet mask on wafer printability by scanning probe microscope (SPM) is well studied. However, only a few experimental results on the measurement accuracy of the phase defect size have been reported. Therefore, in this study, the measurement repeatability of the phase defect volume using SPM and the influence of the defect volume distribution on defect detection signal intensity (DSI) using an at-wavelength dark-field defect inspection tool were examined. A programmed phase defect mask was prepared, and a defect size measurement repeatability test was conducted using an SPM. As a result, the variation of the measured volume due to the measurement repeatability was much smaller than that of the defect-to-defect variation. This result indicates that measuring the volume of each phase defect is necessary in order to evaluate the defect detection yield using a phase defect inspection tool and wafer printability. In addition, the images of phase defects were captured using an at-wavelength dark-field inspection tool from which the defect DSIs were calculated. The DSI showed a direct correlation with the defect volume.

A new strategy for defect inspection by the virtual inspection in semiconductor wafer fabrication

The defect of process equipments is a major factor that impairs the yields in the mass production of semiconductor wafer fabrication and it is a main supervision means to use high-resolution defect inspection tools to detect and monitor the defect damage. Due to the high investment costs of these inspection tools and the resulting decrease in the throughput, how to improve the sampling rate is an important issue for the associated inspection strategy. This paper proposes a new concept and implementation of virtual inspection (VI) to enhance the detection and monitoring of defect in semiconductor production process. The underlying theory of the VI concept is that the state variables identifications (SVIDs) of process equipments can reflect the process quality effectively and loyally. The approach of VI is to combine the application of the fault detection and classification (FDC), and the defect library and the re-engineering of inspection procedure to reach the full-scope of strategic objective. VI enables the defect monitoring to enter a new era by promoting the monitoring level of defect inspection from the previous lot-sampling basis to the wafer-sampling level, and hence upgrades the sampling strategy from random-sampling to full and right-sampling. In this study, various typical defect cases are utilized to illustrate how to create VI models and verify the reliability of the proposed approach. Furthermore, a feasible architecture of the VI implementation for mass production in semiconductor factory is presented in the paper.

Scenario for a Yield Model Based on Reliable Defect Density Data and Linked to Advanced Process Control

Currently, yield enhancement and APC (advanced process control) systems operate independently within the manufacturing process. Yield enhancement has several requirements such as the root cause analysis of yield loss, the reliability of defect density data, and the demand for a link between yield models and APC. For root cause studies chemical analysis uses different preparation techniques to describe the nature and location of contamination or defect densities, e.g. copper bulk contamination or wafer edge effects. The reliability of defect density data and the matching of defect inspection tools improve by the reduction of noise. In combination with a process model this is the prerequisite to set up a random defect-based yield scenario which describes single processes. The combination of this scenario with methods for data acquisition and tracking from APC enhances the prediction of yield.

Expansion of an institutional quality control program at a comprehensive cancer center

The defect of process equipments is a major factor that impairs the yields in the mass production of semiconductor wafer fabrication and it is a main supervision means to use high-resolution defect inspection tools to detect and monitor the defect damage. Due to the high investment costs of these inspection tools and the resulting decrease in the throughput, how to improve the sampling rate is an important issue for the associated inspection strategy. This paper proposes a new concept and implementation of virtual inspection (VI) to enhance the detection and monitoring of defect in semiconductor production process. The underlying theory of the VI concept is that the state variables identifications (SVIDs) of process equipments can reflect the process quality effectively and loyally. The approach of VI is to combine the application of the fault detection and classification (FDC), and the defect library and the re-engineering of inspection procedure to reach the full-scope of strategic objective. VI enables the defect monitoring to enter a new era by promoting the monitoring level of defect inspection from the previous lot-sampling basis to the wafer-sampling level, and hence upgrades the sampling strategy from random-sampling to full and right-sampling. In this study, various typical defect cases are utilized to illustrate how to create VI models and verify the reliability of the proposed approach. Furthermore, a feasible architecture of the VI implementation for mass production in semiconductor factory is presented in the paper.

Defect Review at 0.25 Micron Electron Optic Requirements and Practical Examples

The sub-micron era in 1C process technology has been characterized by ever shrinking device geometries. When the minimum feature size of 0.5 micron was reached, a significant inflection in the usefulness of optical microscopy occurred. Seemingly routine Fab activities such as the use of the optical microscopes to determine the quality of the metal etch were no longer possible. At the same time, an increased use of defect inspection tools such as KLA and Tencor was required to insure stable process quality. These and other factors combined to hasten the introduction of multiple defect review scanning electron microscopes into the modern 1C Fab. This trend has accelerated during the process development of 0.25 micron technology. Accordingly, as leading 1C manufactures introduce production 0.25 devices, it is not unusual to find as many as six such instruments installed in a modern development or fabrication facility. As such, these instruments, commonly called Defect Review Tools (DRT's) constitute an increasing share of the Fab equipment set.