Defect Disposition Research Articles

Computational metrology and inspection (CMI) in mask inspection, metrology, review, and repair

Abstract Mask manufacturers will be impacted by two significant technology requirements at 22 nm and below: the first is the more extensive use of resolution enhancement technologies (RET), such as aggressive optical proximity correction (OPC), inverse lithography technology (ILT), and source mask optimization (SMO); the second is the extreme ultraviolet (EUV) technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. The EUV actinic inspection and AIMS™ will not be available for at least a few years, which make the EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational metrology and inspection (CMI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CMI applications are presented and discussed.

Methods to reduce lithography costs with reticle engineering

The overall decision to manufacture a new VLSI device is nominally dictated by return on investment, with the largest cost driver being design costs. However once a design is released for manufacturing, manufacturing costs are continually scrutinized to reduce overall cost per bit. Typical reticle costs for 45 nm devices are projected to exceed well over $1.5 M USD per set. This cost severely hampers product development, restricting development to the highest return parts. By reducing reticle costs, a greater number of products can meet the typical ROI targets. This paper discussed the various methods for reducing reticle costs for short run products. While the largest component of reticle cost is a result of the increased write and inspect times (including defect disposition), these components can minimized be without incurring a significant impact to overall lithography costs. The effects of different steps in the flow from design tape-out to final wafer will be described and analyzed for effects on net costs.