Methods to reduce lithography costs with reticle engineering

Abstract

The overall decision to manufacture a new VLSI device is nominally dictated by return on investment, with the largest cost driver being design costs. However once a design is released for manufacturing, manufacturing costs are continually scrutinized to reduce overall cost per bit. Typical reticle costs for 45 nm devices are projected to exceed well over $1.5 M USD per set. This cost severely hampers product development, restricting development to the highest return parts. By reducing reticle costs, a greater number of products can meet the typical ROI targets. This paper discussed the various methods for reducing reticle costs for short run products. While the largest component of reticle cost is a result of the increased write and inspect times (including defect disposition), these components can minimized be without incurring a significant impact to overall lithography costs. The effects of different steps in the flow from design tape-out to final wafer will be described and analyzed for effects on net costs.