A SiC trench MOSFET with an enhanced vertical RESURF effect is proposed and analyzed in this article. The device features a deep oxide trench surrounded by a P-type doping layer at the source-side. With the assistant depletion effect of the P-type layer, the concentration of the N-drift region is increased and the specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) is thus reduced. The P-type doping can significantly reduce the intensity of the electric field at the gate oxide corner, and modulate the bulk electric field for the device. The breakdown voltage (BV) is therefore improved. As a result, the proposed SiC MOSFET has a better trade-off of BV and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> . The R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> decreases by 59% and the BV increases by 16% for the proposed device without a CSL layer compared with the conventional trench MOSFET with a CSL layer. Meanwhile, the device exhibits a lower gate-to-drain charge (Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) which is reduced by 52% and the switching loss is also reduced by 19%.