Deep-submicrometer CMOS Processes Research Articles

All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise

We present the first all-digital LTE transmitter (TX) using programmable digital attenuation of receive band (RX-band) noise. The system is architectured to fully exploit the speed and low cost of DSP logic in deep-submicrometer CMOS processes, without increasing at all the design effort of the RF circuitry. To achieve operation without surface acoustic wave filter, the TX uses digital bandpass delta–sigma modulation and mismatch-shaping to attenuate the DAC noise at a programmable duplex distance. These functions can be implemented entirely within DSP, thus taking advantage of the standard digital design methodology. Furthermore, the fully digital RX-band noise shaping significantly relaxes the performance requirements on the RF front-end. Therefore, 10 bits of resolution for the D/A conversion are sufficient to achieve −160 dBc/Hz out-of-band (OOB) noise, without need for digital predistortion, calibration, or bulky analog filters. The TX was fabricated in 28-nm CMOS, and occupies only 0.82 mm2. Besides low OOB noise, our system also demonstrates state-of-art linearity performance, with measured CIM3/CIM5 below −67 dBc, and adjacent-channel leakage ratio of −61 dBc with LTE20 carrier. The circuit consumes 150 mW from 0.9-/1.5-V supplies at +3 dBm output power.

RF Built-in Self Test of a Wireless Transmitter

RF frequency synthesizers and transmitters for wireless system-on-chips have recently migrated to low-cost deep-submicrometer CMOS processes that facilitate all-digital implementations. In addition to all the benefits of lower power, lower silicon cost, reduced board area, and improved performance that the scaled CMOS integration entails, the testing costs for RF performance and wireless standard compliance could also be drastically reduced. In this brief, we propose a built-in self test (BIST) method, which is based on the premise that the internal frequency synthesizer and transmitter signals are in digital format allowing for digital signal processing to ascertain the RF performance without external test equipment. With the RF BIST capability, millions of SoCs can be calibrated and tested in a production environment using a low cost digital tester while benefiting from increased test coverage and reduced test time and cost. The presented techniques have been successfully implemented in two generations of commercial digital RF processors: 130-nm Bluetooth and 90-nm GSM single-chip radios

A 1 V Phase Locked Loop with Leakage Compensation in 0.13 m CMOS Technology

In deep sub-micrometer CMOS process, owing to the thin gate oxide and small subthreshold voltage, the leakage current becomes more and more serious. The leakage current has made the impact on phase-locked loops (PLLs). In this paper, the compensation circuits are presented to reduce the leakage current on the charge pump circuit and the MOS capacitor as the loop filter. The proposed circuit has been fabricated in 0.13-μm CMOS process. The power consumption is 3 mW and the die area is 0.27 x 0.3 mm 2 .

Survey of noise performances and scaling effects in deep submicrometer CMOS devices from different foundries

Submicrometer CMOS technologies provide well-established solutions to the implementation of low-noise front-end electronics for a wide range of detector applications. Since commercial CMOS processes maintain a steady trend in device scaling, it is essential to monitor the impact of these technological advances on the noise parameters of the devices. In this paper we present the results of an extensive analysis carried out on CMOS transistors fabricated in 0.35, 0.25, and 0.18 mum technologies from different foundries. This allows us to evaluate the behavior of 1/f and channel thermal noise parameters with different gate oxide thickness and minimum channel length and to give an estimate of their process-to-process spread. The experimental analysis is focused on actual device operating conditions in monolithic detector readout systems. This means that moderate or weak inversion are often the only relevant regions for front-end devices. To account for different detector requirements, the noise behavior of devices with different geometries and input capacitance was investigated. The large set of data gathered from the measurements provides a powerful tool to model noise parameters and establish front-end design criteria in deep submicrometer CMOS processes

SoC with an integrated DSP and a 2.4-GHz RF transmitter

We present a system-on-chip (SoC) that integrates a TMS320C54x digital signal processor (DSP), which is commonly used in cellular phones, with a multigigahertz digital RF transmitter that meets the Bluetooth specifications. The RF transmitter is tightly coupled with the DSP and is directly mapped to its address space. The transmitter architecture is based on an all-digital phase-locked loop (ADPLL), which is built from the ground up using digital techniques and digital creation flow that exploit high speed and high density of a deep-submicrometer CMOS process while avoiding its weaker handling of voltage. The frequency synthesizer features a wideband frequency modulation capability. As part of the digital flow, the digitally controlled oscillator (DCO) and a class-E power-amplifier are created as ASIC cells with digital I/Os. All digital blocks, including the 2.4-GHz logic, are synthesized from VHDL and auto routed. The use of VHDL allows for a tight and seamless integration of RF with the DSP. To take advantage of the direct DSP-RF coupling and to demonstrate a software-defined radio (SDR) capability, a DSP program is written to perform modulation of the GSM standard. The chip is fabricated in a baseline 130-nm CMOS process with no analog extensions and features high logic gate density of 150 kgates per mm/sup 2/. The RF transmitter area occupies only 0.54 mm/sup 2/, and the current consumption (including the companion DSP) is 49 mA at 1.5-V supply and 4 mW of RF output. This proves attractiveness and competitiveness of the "digital RF" approach, whose goal is to replace RF functions with high-speed digital logic gates.

A deep submicrometer CMOS process compatible high-Q air-gap solenoid inductor with laterally laid structure

A high-quality (Q) on-chip solenoid inductor has been fabricated by 0.18 mm CMOS technology with air-gap structure. The solenoid structure with laterally laid out structure saves the chip area significantly and the air-gap suppresses the parasitic capacitances to obtain high-Q value. Additionally, with software ANSYS simulation, the solenoid inductor also possesses a higher strength for impact (80 000 times) in comparison to a spiral inductor. The measured peak-Q and peak-Q frequency with an air-gap are 8.8 and 1.7 GHz, respectively, which present almost 9% improvements in the magnitude and 54% in the peak-Q frequency in comparison to the conventional solenoid inductor at 8.1 and 1.1 GHz.

Phase-domain all-digital phase-locked loop

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator that deliberately avoids any analog tuning controls. When implemented in a digital deep-submicrometer CMOS process, the proposed architecture appears more advantageous over conventional charge-pump-based phase-locked loops (PLLs), since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. An actual implementation of an all-digital PLL (ADPLL)-based local oscillator and transmitter used in a commercial 0.13-/spl mu/m CMOS single-chip Bluetooth radio has recently been disclosed. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. Due to the lack of the correlational phase detection mechanism, the loop does not contribute to the reference spurs. The measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications. In this paper, we present the mathematical description and operational details of the phase-domain ADPLL.

Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits

This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel 4-2 and 5-2 compressor designs, are prototyped and simulated to evaluate their performance in speed, power dissipation and power-delay product. The newly developed circuits are based on various configurations of the novel 5-2 compressor architecture with the new carry generator circuit, or existing architectures configured with the proposed circuit for the exclusive OR (XOR) and exclusive NOR ( XNOR) [XOR-XNOR] module. The proposed new circuit for the XOR-XNOR module eliminates the weak logic on the internal nodes of pass transistors with a pair of feedback PMOS-NMOS transistors. Driving capability has been considered in the design as well as in the simulation setup so that these 4-2 and 5-2 compressor cells can operate reliably in any tree structured parallel multiplier at very low supply voltages. Two new simulation environments are created to ensure that the performances reflect the realistic circuit operation in the system to which these cells are integrated. Simulation results show that the 4-2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.

Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process

A novel digitally controlled oscillator (DCO)-based architecture for frequency synthesis in wireless RF applications is proposed and demonstrated. It deliberately avoids any use of an analog tuning voltage control line. Fine frequency resolution is achieved through high-speed /spl Sigma//spl Delta/ dithering. Other imperfections of analog circuits are compensated through digital means. The presented ideas enable the employment of fully-digital frequency synthesizers using sophisticated signal processing algorithms, realized in the most advanced deep-submicrometer digital CMOS processes which allow almost no analog extensions. They also promote cost-effective integration with the digital back-end onto a single silicon die. The demonstrator test chip has been fabricated in a digital 0.13-/spl mu/m CMOS process together with a DSP, which acts as a digital baseband processor with a large number of digital gates in order to investigate noise coupling. The phase noise is -112 dBc/Hz at 500-kHz offset. The close-in spurious tones are below -62 dBc, while the far-out spurs are below -80 dBc. The presented ideas have been incorporated in a commercial Bluetooth transceiver.

Advances in silicon-on-insulator optoelectronics

Recent developments in silicon based optoelectronics relevant to fiber optical communication are reviewed. Silicon-on-insulator photonic integrated circuits represent a powerful platform that is truly compatible with standard CMOS processing. Progress in epitaxial growth of silicon alloys has created the potential for silicon based devices with tailored optical response in the near infrared. The deep submicrometer CMOS process can produce gigabits-per-second low-noise lightwave electronics. These trends combined with economical incentives will ensure that silicon-based optoelectronics will be a player in future fiber optical networks and systems.