Deep N-well Research Articles

High-Voltage CMOS Active Pixel Sensor

The high-voltage CMOS (HVCMOS) sensors are a novel type of CMOS active pixel sensors for ionizing particles that can be implemented in CMOS processes with deep n-well option. The pixel contains one sensor electrode formed with a deep n-well implanted in a p-type substrate. CMOS pixel electronics, embedded in shallow wells, are placed inside the deep n-well. By biasing the substrate with a high negative voltage and by the use of a lowly doped substrate, a depleted region depth of at least 30 μm can be achieved. The electrons generated by a particle are collected by drift, which induces fast detectable signals. This publication presents a 4.2-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> large HVCMOS pixel sensor implemented in a commercial 180-nm process on a lowly doped substrate and its characterization.

Using Schottky Barrier Diode to Improve Latch-Up Immunity for CMOS ICs Operating With Negative Voltage Sources

For some applications, the CMOS ICs need to be supplied with positive and negative voltage sources for the desired circuit operations. To supply the negative voltage source for circuit operations in the silicon chip with the common p-type substrate grounded, the isolation rings configured with n-well (NW) and deep n-well (DNW) layers must be used to isolate the circuits of nMOS devices operating with negative voltage from the common P-substrate. Such NW/DNW isolation rings in the circuit layouts are often connected to ground (GND =0V) for the circuit operations with negative voltage source. But, a parasitic p-n-p-n path from I/O pMOS to this grounded NW/DNW isolation ring may cause the circuits at high risk to latch-up. In this letter, a novel method to improve latch-up immunity against such parasitic p-n-p-n path by using a Schottky junction is reported.

A fully integrated multiphase switched-capacitor DC-DC converter with PFM control and charge sharing loss reduction

A fully integrated high efficiency switched-capacitor (SC) DC-DC converter with pulse frequency modulation (PFM) control is presented. The small signal model of the multiphase-interleaving SC converter is given and it is verified through the simulation and the measurement results. For high efficiency, this design set the dominant pole at the output of the error amplifier (EA) and the 14-phase interleaving topology can push the non-dominant pole away from the Unit Gain Frequency (UGF) for the loop stability. By combining the flying-well and the deep n-well (DNW) isolation techniques, the proposed high-density MOS capacitor can reduce both the parasitic loss and the charge sharing loss of the converter. The conversion ratio of the converter is 2:1 under 3.3V power supply. This SC DC-DC converter is fabricated in the 40 nm CMOS process. It obtains the peak efficiency of 86.2% and the output power-density of 226 mW/mm2. It maintains the efficiency above 80% from 8 mA to 50 mA load condition.

Sensitivity Improvement of a Fully Symmetric Vertical Hall Device Fabricated in 0.18 μm Low-Voltage CMOS Technology

This paper proposes a new implementation method to significantly improve the magnetic sensitivity of a fully symmetric vertical Hall device (FSVHD) based on low-voltage CMOS technology. The FSVHD consists of four identical three-contact vertical Hall elements (3CVHE) and each 3CVHE is located in a low-doped deep n-well. The terminals of the 3CVHE are $\text{n}^{+}$ implanted in an n-well and a $\text{p}^{+}$ implantation in a p-well is performed to act as a trench between two adjacent $\text{n}^{+}$ contacts, enabling Hall current flowing deeply for sensitivity improvement. The influence of the geometry sizes on magnetic sensitivity is exploited utilizing TCAD simulation to obtain the optimized device structure in a $0.18~\mu\text{m}$ CMOS standard technology. The experimental results reveal that the proposed FSVHD with a $\text{p}^{+}$ /p-well trench can attain an improved voltage-related sensitivity of 8.4 mV/VT, which is about 70% higher than that of a conventional FSVHD without a trench in the same CMOS fabrication process, while offset and noise are not degraded. The proposed $\text{p}^{+}$ /p-well implantation trench is a good solution to enhance the sensitivity of a low-voltage CMOS VHD with a low manufacturing cost.

A 5.43 nV/√Hz Chopper Operational Amplifier Using Lateral PNP Input Stage with BJT Current Mirror Base Current Cancellation

This paper presents a low-noise chopper operational amplifier using a lateral PNP input stage with bipolar junction transistor (BJT) current mirror base current cancellation. The BJT has a lower noise characteristic than the metal–oxide–semiconductor (MOS) transistor, where low-noise characteristics can be achieved by implanting the BJT to the input stage of the amplifier; however, the base current of the BJT input stage causes low input impedance of the amplifier. The BJT current mirror base current cancellation technique is implemented to enhance the input impedance of the BJT input stage by canceling the base current. BJT current mirror base current cancellation is implemented with a simple scheme using NPN transistors with deep n-well in a generic complementary metal–oxide–semiconductor (CMOS) process. For further noise reduction with the BJT input stage, a chopper amplifier scheme is adopted to reduce low-frequency components such as 1/f noise terms in the low-frequency range. The prototype chip is fabricated in a 0.18-μm CMOS process. The active area of the prototype amplifier is 0.213 mm2. The measured input-referred noise is 5.43 nV/√Hz. The measured input base current of the amplifier with base current cancellation is 67.971 nA. The total amplifier current consumption is 278.3 μA, with a power supply of 3.3 V.

Test results of ATLASPIX3 — A reticle size HVCMOS pixel sensor designed for construction of multi chip modules

High voltage CMOS pixel sensors will be or are proposed to be used in several particle physics experiments for particle tracking like Mu3e experiment. ATLASPIX3 is the first full reticle size monolithic HVCMOS sensor for construction of multi-chip modules. The specifications for the use case have been taken from ATLAS pixel upgrade in fifth layer where it was a candidate for. The size of the chip is 2.0×2.1 cm2 with periphery at one side which makes the chip 3-side buttable. ATLASPIX3 has been implemented in a standard 180 nm HVCMOS process. Each pixel has an area of 150×50μm2 and contains a large charge collecting electrode implemented as deep n-well. The depleted volume around the n-well is enlarged by a high voltage bias and the usage of higher resistivity substrate. The readout electronics supports both triggered and triggerless readout with zero-suppression. ATLASPIX3 could be used for the construction of CMOS modules for particle tracking in experiments where high time resolution, high radiation tolerance, low power and low material budget are required. In the design phase, special attention has been paid to decreasing timing differences between pixels and the rate capability of the readout.

Design of High-Efficiency SPADs for LiDAR Applications in 110nm CIS Technology

Single photon avalanche diodes (SPADs) featuring a high detection rate of near-IR photons are much desired for outdoor LiDAR based on direct time-of-flight (ToF). This article presents the complete design flow of a SPAD detector for LiDAR. First, the selection of the emitter wavelength is discussed, considering the maximum allowed power underlying eye safety regulations, solar irradiance, and reflected signal power. Then, the choice of the SPAD structure is discussed based on the TCAD simulation of quantum efficiency and crosstalk. Next, the proposed P-well/ Deep N-well SPAD is explained. The electro-optical characterization of the detectors is presented as well. The performance of the time-of-flight image sensors is determined by the characteristics of the individual SPADs. To fully characterize this technology, devices with various sizes, shapes, and guard ring widths have been fabricated and tested. The measured mean breakdown voltage is 18 V. The proposed structure has a 0.4 Hz/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dark count rate and 0.5% afterpulsing. The FWHM (total) jitter and photon detection probability at 850nm wavelength are of 92 ps and 10%. All figures have been measured at 3 V excess voltage. Finally, the performance of the SPAD detector is analyzed by evaluating the signal-to-noise ratio at different acquisition times. Distance ranging measurements have been performed, achieving a depth resolution of 1 cm up to 6.3 m range.

PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications

This article presents two novel structures for designing current mode logic (CML) digital circuits [MOS CML (MCML) and multiple tail CML (MTCML)] in ultralow-power (ULP) and high-speed (HS) applications. The transistor’s bulk can be used as a digital signal input at a level, where it does not cause a disturbance to the operation of the transistor. Therefore, the number of transistors used in novel structures is reduced and it is possible to improve power delay product (PDP) and time propagation delay (TPD) in some of the tail currents. This technique is obtained through integrating the bulk-driven technique into the CML digital circuits, which are in the form of bulk-driven MCML (BD-MCML) and BD-MTCML. In the conventional CMOS technology, the proposed structures depend on the type of substrate. The BD-MCML structure uses a deep n-well technology and the BD-MTCML uses an n-well technology. The CML gates, such as AND, XOR, and D-latch, are suggested. The systematic use of the proposed structures is discussed in both HS and ULP applications. Finally, an unsigned multiplier is designed in the form of the BD-MTCML with a conventional 180-nm technology. Mixed-signal circuits are Serial/De-serial (SerDes), optical receivers, radio frequency (RF) receivers, and line drivers on the HS approach, and also video processors and A/D and D/A converters on the ULP approach.

A Sub-200nW All-in-One Bandgap Voltage and Current Reference Without Amplifiers

This brief presents a low-power and high-precision bandgap voltage and current reference (BGVCR) in one simple circuit for battery-powered applications. All the amplifiers have been eliminated in the proposed circuit. The voltage reference is derived from the bandgap topology, and the current reference is obtained by summing a proportional-to-absolute-temperature (PTAT) current and a complementary-to-absolute-temperature (CTAT) current. Therefore, the temperature coefficient of the current reference can be optimized. Besides, a pseudo-cascode structure and a simple line sensitivity enhancement circuit are adopted to improve the current mirror accuracy and line sensitivity. The proposed circuit is fabricated in a 0.18-μm deep N-well CMOS process with an active area of 0.063 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured VREF and IREF are 1.2 V and 51 nA, respectively. The VREF and IREF show measured average temperature coefficients of 32.7 ppm/°C and 89 ppm/°C at a temperature of -45 to 125°C and standard deviations of 0.17 % and 1.15 %, respectively. In the supply voltage range of 2 to 5 V, the line sensitivities of voltage and current are 0.058%/V and 1.76%/V, respectively. The minimum supply voltage is 2 V with a total power consumption of 192 nW at room temperature.

Radiation hard DMAPS pixel sensors in 150 nm CMOS technology for operation at LHC

Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s employing silicon substrate with a thin epitaxial layer in which deposited charge is collected by disordered diffusion rather than by drift in an electric field. As a consequence the signal is small and slow, and the radiation tolerance is below the requirements for LHC experiments by factors of 100 to 1000. We developed fully depleted (D)MAPS pixel sensors employing a 150 nm CMOS technology and using a high resistivity substrate as well as a high biasing voltage. The development has been carried out in three subsequent iterations, from prototypes to a large pixel matrix comprising a complete readout architecture suitable for LHC operation. Full CMOS electronics is embedded in large deep n-wells which at the same time serve as collection nodes (large electrode design). The devices have been intensively characterized before and after irradiation employing lab tests as well as particle beams. The devices can cope with particle rates seen by the innermost pixel detectors of the LHC pp-experiments or as seen by the outer pixel layers of the planned HL-LHC upgrade. They are radiation hard to particle fluences of at least 1015 neq/cm2 and total ionization doses of at least 50 Mrad.

Mix‐mode forward‐biased diode with low clamping voltage for robust ESD applications

The forward-biased diode has been widely applied in electrostatic discharge (ESD) protection projects. In this Letter, various diodes with finger-shaped topology are studied by transmission line pulse (TLP) and emission microscope (EMMI) experiments. Among them, a novel mix-mode diode with P-well and floating deep N-well, called MMDIO, is fabricated by the same process and footprint, except that some discrete N+ regions are being added to the original anode P+ region. This approach forms a combination of a parasitic NPN transistor and a PNPN structure, which can significantly optimise the ESD current efficiency and clamping voltage (V CL). According to the comprehensive comparison, the MMDIO with overlapped anode N+ layout could endure the failure current 1.25 times higher than that of a regular diode under the same junction capacitance (C j), while the V CL is reduced by 20%. Accordingly, the MMDIO is an attractive solution to pass the higher ESD level without any negative influence.

Measured effectiveness of deep N-well substrate isolation in a 65 nm pixel readout chip prototype

The same charge sensitive preamplifier and discriminator circuit with different isolation strategies has been tested to compare the isolation of both analog and digital circuits from the substrate of a 65 nm bulk CMOS process to the isolation of only digital circuits, tying analog ground locally to the substrate. This study will show that the circuit with analog on the substrate and digital in deep N-well has better noise isolation between analog and digital.

A comparative study of stacked-diode configurations operating in the photovoltaic region

This article presents a detailed comparative analysis of two possible stacked-diode configurations operating as solar cells. The performance of a single p-well – deep n-well diode is compared with the combination of such diode with a n-diff – p-well diode in parallel. Both configurations occupy the same area but offer different performance and, accordingly, they can have different application scopes. A test circuit to gauge the diodes performance and their spectral sensitivity has been integrated along with the two diode configurations in a $0.18~\mu \text{m}$ CMOS standard fabrication technology. The measured experimental results for the two diode configurations under study are validated with an analytical diode physical model.

A Tunable SiGe BiCMOS Gain-Equalizer For X-Band Phased-Array RADAR Applications

This brief presents a compact-size tunable gain-equalizer for X-band phased-array RADAR applications in a 0.25- $ \mu \text{m}$ SiGe BiCMOS technology. An isolated nMOS-based variable resistance was used for the first time to tune the slope of the gain-equalizer. For nMOS, an isolated body created by a deep n-well was utilized to reduce insertion loss due to the substrate conductivity. Furthermore, the power-handling capability of the tunable gain-equalizer was improved thanks to the resistive body-floating technique. The designed tunable gain-equalizer operates in the frequency range from 8 to 12.5 GHz with a measured positive slope of 1 dB/GHz and 1 dB tunable slope. The effective chip area excluding the pads is 0.21 mm2, and the total area including pads is 0.31 mm2. To authors best knowledge, this brief is the first tunable gain-equalizer in SiGe technology presented for X-band phased-array RADAR applications.

An ultra-low-power low-noise amplifier using cross-coupled positive feedback for 5G IoT applications

The wireless communication in the next generation is bound to be driven by massive machine-type communication or in other words Internet-of-things (IoT). In the near future, the need for effective communication and higher data processing rates will require IoT devices to support 5G networks. For 5G IoT applications in the ultra-wideband range (3.1–10.6 GHz), the analog receivers must provide both high-performance and energy efficiency simultaneously. This work addresses the demands of 5G IoT analog receivers by proposing an ultra-low-power low noise amplifier (LNA) employing cross-coupled positive shunt feedback. The proposed LNA is designed in UMC 180 nm deep n-well process, and the post-layout characterization is done using Cadence SpectreRF. The proposed design achieves a peak gain of 9.94 dB and a noise figure of 3.2–1.086 dB along the usable bandwidth of 3.2–9.625 GHz while consuming an ultra-low-power of 493 µW from a 1-V power supply. The maximum input-referred third-order intercept point of 8.81 dBm is attained for an input signal at 2.4 GHz and the interferer as close as 2.425 GHz. The LNA consumes a minimal layout area of only 676.2 µm × 350.7 µm. The proposed LNA has the better figure-of-merit while consuming almost 50% less power than the recently reported sub-mW LNA in literature.

Radiation hard active pixel sensor with [formula omitted][formula omitted][formula omitted] pixel size designed for capacitive readout with RD53 ASIC

A new concept for a capacitively coupled particle detector (CCPD) is described. Sensor and readout chips are attached using a small number of large bumps. A sensor chip for such a CCPD has been designed and tested. The sensor chip is based on the HVCMOS structure. Deep n-well is used as the charge collecting electrode. To allow strong amplification, which is necessary for chip to chip signal transmission, a novel CMOS based comparator with rail to rail output swing has been implemented in each pixel. The pixel outputs are connected to transmitting electrodes implemented in the top metal layer of the sensor chip. Using special address encoding a group of 16 pixels is connected to 8 transmitting electrodes. The pixel size is 25μm×50μm and the transmitting electrode pitch is 50μm×50μm. Therefore a standard HL-LHC readout chip developed by RD53 collaboration can be used for readout of the sensor.

3.3V DC output at -16dBm sensitivity and 77% PCE rectifier for RF energy harvesting

&lt;span&gt;This paper presents a high voltage conversion at high sensitivity RF energy harvesting system for IoT applications. The harvesting system comprises bulk-to-source (BTMOS) differential-drive based rectifier to produce a high efficiency RF energy harvesting system. Low-pass upward impedance matching network is applied at the rectifier input to increase the sensitivity and output voltage. Dual-oxide-thickness transistors are used in the rectifier circuit to maintain the power efficiency at each stage of the rectifier. The system is designed using 0.18µm Silterra RF in deep n-well process technology and achieves 4.07V output at -16dBm sensitivity without the need of complex auxiliary control circuit and DC-DC charge-pump circuit. The system is targeted for urban environment.&lt;/span&gt;

Performance of the ATLASPix1 pixel sensor prototype in ams aH18 CMOS technology for the ATLAS ITk upgrade

Monolithic active pixel sensors (MAPS) based on commercial high-voltage CMOS processes are an exciting technology that is considered as an option for the ATLAS Inner Tracker upgrade. Particles are detected using deep n-wells on a p-type substrate as sensor diodes with the depleted region extending into the silicon bulk. With readout electronics and sensor integrated on the same device, the detector complexity and the material budget are greatly reduced. The ATLASPix1 pixel sensor prototype is a large-scale MAPS prototype that implements the full readout chain on a single physical chip. It features a large in-pixel sensor electrode and is produced using the ams aH18 high voltage technology. Three pixel matrices with different readout architectures, triggered and untriggered, and pixel designs are implemented. We show the performance of one of the pixel matrix variants for samples irradiated up to 1015 1MeV meq/cm2.

High-Voltage ESD Protection Device With Fast Transient Reaction and High Holding Voltage

A stacked p-n-p(s) and grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) solution, with higher holding voltage ( ${V}_{H}$ ) and faster transient reaction than a p-n-p-embedded SCR, is proposed for high-voltage (HV) applications. The lowering of the beta gain ( $\beta$ ) of the p-n-p by the use of a deep-N-well (DNW)-based p-n-p in the proposed ESD device is a key to weakening the parasitic SCR action and results in an increase of ${V}_{H}$ . A lower voltage overshoot and fast transient reaction in a charged device model (CDM) event are due to the ggNMOS (parasitic n-p-n). The trigger and ESD shunting mechanisms are determined by the p-n-p(s) in series with the ggNMOS. This is an attractive configuration for achieving an effective, HV ESD device with high ${V}_{H}$ and low-voltage overshoot under CDM conditions.

Design and optimization of 30 V fully isolated nLDMOS with low specific on-resistance for HVIC applications

In this paper, a novel 30 V fully isolated n-channel lateral DMOS (nLDMOS) with low specific on-resistance (RON,sp) is proposed and experimentally realized using 0.35 µm Bipolar-CMOS-DMOS (BCD) process. We optimized the process parameters, such as doping concentration of the high-voltage drift n-well (HVNW) layer, P-buried layer (PBL) and pre deep n-well (Pre-DNW) layer, for achieving a superior tradeoff between high breakdown voltage (BV) and the low RON,sp. The proposed nLDMOS is fully isolated from the substrate to support negative bias to drain and has a very lower RON,sp than other competitors in the similar technology, which is critical for devices used in high-voltage, high-current switching applications such as HVIC's. The fabricated device exhibits a BV of 42 V with RON,sp as low as 15 mohm-mm2 . Besides, the new structure is fully compatible with standard 0.35 µm BCD technology, with a margin of up to 15% in process variation, which is large enough to meet the industrial requirement for mass production. Hence, it is not only high performance but also a low-cost solution.