Drain Current Decreases Research Articles

A steady state drain current technique for generation and recombination lifetime measurement in the SOI MOSFET

A new steady state drain current technique is developed for both the generation and recombination lifetime extraction in the fully-depleted (FD) SOI MOSFET. At all times during the measurement, the device has one silicon surface maintained in strong accumulation, and the other surface in strong inversion. The accumulation layer is modulated with a negative ramp voltage applied to the gate, so that more holes are demanded by the accumulation layer (n-channel enhancement MOSFET). When the demand for the additional holes cannot be met by generation in the bulk of the silicon film, electrons from the inversion region have to be expelled, resulting in a decrease in the external drain current. The drain current saturates when the rate of demand for additional holes is balanced by the rate of hole generation. From the measured saturation drain current, together with the given ramp rate, the generation lifetime can be easily determined. A positive ramp voltage is used to extract recombination lifetime. As a nonpulse technique, only steady state parameters are measured. The technique has the added advantage of simplicity in the interpretation of the results.

Impact of induced lattice defects on performance degradation of AlGaAs/GaAs p-HEMTs

Irradiation damage and its recovery behavior resulting from thermal annealing in AlGaAs/GaAs pseudomorphic HEMTs, subjected to 1-MeV electrons, 1-MeV fast neutrons and 220-MeV carbon, are studied. The drain current and effective mobility decrease after irradiation, while the threshold voltage increases in positive direction. The decrease of the mobility is thought to be due to the scattering of channel electrons with the induced lattice defects and also to the decrease of the electron density in the two-dimensional electron gas (2DEG) region.

Progress in the use of 4H-SiC semi-insulating wafers for microwave power MESFETs

The use of Silicon Carbide semi-insulating wafers has to be mastered in order to reach output power densities up to 3–4 W mm −1 in the 1–2 GHz frequency range (values that are currently targeted). This study shows that the buffer layer doping level and thickness have a great influence on the MESFET behavior. We have studied three epilayer configuration on SI substrates that differ only by the buffer layer. On two of them, a slow drain current decrease in d.c. mode was observed. On the third one, no d.c. current drift was observed without rf input power, but drain current decreases instantaneously when rf input power is switched on. Traps, located either in the buffer layer or in the substrate are supposed to be responsible for these drift phenomena. Load–pull measurements were performed at 2 GHz on transistors fabricated on the three different structures. One of them, with a 2 mm gate periphery, has been measured under 72 V drain–source bias voltage and 2.1 W mm −1 power density was obtained at 2 GHz. We believe these results are the first to be published on a SiC MESFET with d.c. bias voltage over 70 V.

Impact of high energy particles on InGaP/InGaAs pseudomorphic HEMTs

Irradiation damage and its recovery behavior resulting from thermal annealing in InGaP/InGaAs pseudomorphic HEMTs, subjected to a 20 MeV alpha ray and 220 MeV carbon, are studied for the first time. The drain current and effective mobility decrease after irradiation, while the threshold voltage increases in positive direction. The degradation of device performance increases with increasing fluence. The decrease of the mobility is thought to be due to the scattering of channel electrons with the induced lattice defects and also to the decrease of the electron density in the two dimensional electron gas (2DEG) region. The influence of the radiation source on the degradation and recovery is discussed by comparison with 1 MeV electron and 1 MeV fast neutron exposures with respect to the number of knock-on atoms and the nonionizing energy loss (NIEL). Isochronal thermal annealing for temperatures ranging from 75 to 300/spl deg/C shows that the device performance degraded by the irradiation recovers completely.

Quantum transport andI–Vcharacteristics of quantum size field effect transistor

Quantum electron transport is expected to occur in nanometer-size field effect transistors. We show that the amplitude of the transmitted wave equals 1 only when the electric field in the conducting channel is zero. By reducing the dimension of the quantum transport from bulk to a two-dimensional electron gas system, and further to a one-dimensional quantum wire, the current-bias relation is not affected while the gate control over the drain current weakens. Starting from the Poisson and Schrödinger equations, we have studied numerically the quantum wave transport through the conduction channel where scattering processes are neglected, theI–Vcharacteristic of a typical heterojunction high electron mobility transistor shows a linear relationship between drain current and voltage at low drain bias, but the drain current decreases with increasing drain voltage at a high bias.

Negative photoresponse in modulation doped field effect transistors (MODFET's): theory and experiment

A model for the mechanism of negative photoresponse, namely, the decrease of drain current under illumination, in AlGaAs-GaAs MODFET's is presented. Also, a comprehensive experimental study discussing the dependence of this phenomena on gate and drain to source bias voltages and optical power, as well as a comparison with devices that show the usual positive photoresponse, are reported. The negative photoresponse is attributed to trapping of photogenerated carriers in the GaAs buffer layer, causing a change in the potential profile and consequent reduction in the number of carriers in the 2-DEG channel. The above theory is supported by numerical solution of Poisson's and electron continuity equation, using the finite-elements method. Finally, the implications of the negative photoresponse on the high-speed photodetection properties of MODFET's devices are discussed. >

Frequency dispersion and modulated signal distortion characteristics of gaas power MESFETs at large signal operation

AbstractIn the search for a cause of modulated signal distortion of a GaAs power FET, an analysis is made for the frequency dispersion caused by the surface trap. First, the frequency dispersion characteristics of the Vgs‐Id relationship of the FET under a large signal operation are measured. It is found that the Vgs‐Id characteristics at high frequencies are very different from the one at dc. It is found that the drain current decreases near Vgs = 0 V. Further, simulation is carried out for the intermodulation distortion using the Vgs‐Id characteristics at the high‐frequency region. It is found that an increase in the nonlinearity of the Vgs‐Id characteristic due to frequency dispersion is the cause of increased modulated signal distortion. From the measured temperature dependence of the frequency dispersion of the drain current, energy levels related to the dispersion are found to be 0.56 and 0.19 eV. Further, a comparison is made between SiN and SiO2 surface passivation films. It is found that frequency dispersion is small and a low distortion characteristic can be obtained with the SiN film.

Effect of intensity-modulated optical radiation on the DC characteristics of GaAs MESFETs

The effect of an intensity-modulated optical signal on the characteristics of a MESFET is studied theoretically. At a constant gate voltage, the drain current of the device can be controlled by the incident optical power density and the frequency of the modulating signal. The drain current decreases with increase in modulating signal frequency at constant incident optical power density, while it increases with the increase in incident optical power density for a fixed value of the modulating signal.

Failure mechanisms in life‐tested hemts

AbstractFailure mechanisms in RF life‐tested high electron mobility transistors (HEMTs) were investigated both experimentally and theoretically. As a result of RF life testing the devices degraded by a decrease in drain current, transconductance, and gain and an increase in noise figure. Monte Carlo simulations confirmed the experimental conclusions that degradation resulted from gate metal interdiffusion and ohmic contact degradation.

Failures of ALGaAs/GaAs HEMTs induced by hot electrons

AbstractWe present in this work the rapid and irreversible degradation of electrical characteristics induced by hot electrons in unpassivated AlGaAs/GaAs HEMTs. When devices are biased at high drain‐source voltages carriers can reach high energies and give rise to impact ionization phenomena. Devices biased in these conditions show a decrease of drain current, an increase of parasitic drain resistance and an increase of transconductance frequency dispersion. Degradation has been found proportional to the maximum electric field in the channel. Results suggest that hot electrons generate deep levels in the access region between gate and drain contacts possibly at the interfaces between the semiconductor layers in the gate‐drain region.

Double carrier injection in the sidegating effect in GaAs MESFETs

Double injection into the semi-insulating substrate was investigated as a mechanism of sidegating in GaAs MESFETs. A change of gate current with sidegate voltage and a correlation between abrupt variations in drain, gate, and sidegate currents and instabilities in test devices support a physical model in which a gradual decrease of drain current with a nonlinear potential profile across the substrate is caused by low-level double injection and an abrupt decrease of drain current is caused by high-level double injection.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Scanning tunneling microscopy/spectroscopy of a-Si:H/SiNx interface of thin film transistors

In the deviation of current/voltage characteristics for staggered thin film transistors (TFTs) operating above threshold, previous authors have neglected amorphous silicon and gate insulator (silicon nitride) interface effects. I show that is not sufficient for explaining common TFT behavior. A corrugation at the a-Si/SiNx interface was found. The corrugation width of the a-Si/SiNx interface and the accumulation layer width perpendicular to the interface is comparable for a-Si TFT. The mean free path of free electrons traveling along with this interface is reduced, namely, the mobility decreases. The localized density of states (DOS) in this corrugated interface decreases areal charge density of electrons in extended states so that drain current decrease. These localized DOS trap electrons so that even above threshold the gate-induced electrons could not move, namely, the gate threshold voltage of TFT increases.

GaInAs n-channel inversion-mode MISFET's with improved long- and short-term stability

CVD SiO 2 has been used as gate insulator for GaInAs n-channel inversion-mode MISFET's. By applying a rapid thermal annealing cycle with a maximum temperature of 700°C, the number of fast interface states could be strongly reduced, thus leading to stable device performance in the time range between 10-6and 10 s. The drain current drift for longer times, however, is not affected by the annealing step. A reduction of the dielectric deposition temperature down to 250°C, however, results in improved long-term stability with a drain current decrease of only 5 percent after 104s of operation at room temperature.

Substrate current in short n-channel MOS transistors

Abstract Tho substrain current against gate voltage characteristics or relatively short n-channel MOS transistors were examined for various substrate and drain voltages, channel length and surface doping conditions : namely without implantation, implantation for threshold voltage adjustment and implantation for depletion mode device types A, B and C, respectively. The substrate current may increase or decrease when increasing the aubstrate voltage magnitude duo to the fact that the drain current decreases and the multiplication factor increases with the substrate bias. The substrate current increases when decreasing the channel length. It increases for the devices of type B, but is lower for type C. These experimental results were qualitatively explained by using published models in which the substrate current is caused by low-level impact ionization within the pinched-off region. A simple model in which the ionization coefficient and the field derivative with respect to x wore assumed to be power-law fie...

High-voltage junction-gate field-effect transistor with recessed gates

A new recessed-gate structure for vertical-channel junction field-effect transistors (JFET's) is described together with a self-aligned gate-source process developed to fabricate these devices. Using this technology, devices with groove depths ranging from 8 to 18 µm have been fabricated. The characteristics of these devices is described as a function of the groove depth. It has been found that the devices display pentode-like characteristics at low gate voltages and triode-like characteristics at high gate voltages. The blocking gain has been found to increase with groove depth. However, this is accompanied by an increase in the on-resistance and a decrease in the saturated drain current. Devices with gate breakdown voltages of up to 600 V have been fabricated with the recessed-gate structure. These high-voltage field-effect transistors (FET's) have a unity power gain cutoff frequency of 600 MHz and gate turn-off times of less than 25 ns.