Decoupling Capacitor Research Articles

Characterization of SiC Trench MOSFETs in a Low-Inductance Power Module Package

This paper evaluates the temperature-dependent static and switching characteristics of SiC Trench mosfet s in a low-inductance multiple-chip power module. First, a phase-leg power module package design with integrated decoupling capacitance is proposed and fabricated based on the P-cell/N-cell concept, and the module design including the substrate layout and packaging material selection are discussed. With the fabricated power module, the temperature-dependent static and switching characteristics of the SiC Trench mosfet s are comprehensively investigated, and the key performance differences from the traditional SiC planar mosfet s are discussed. Specifically, compared to the SiC mosfet s with planar structure, the SiC Trench mosfet s are observed to have a different temperature coefficient in term of the turn- off switching loss. Detailed analysis is provided as well to explain the experimental results.

Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices

Low power system-on-chips (SoCs) are now at the heart of Internet-of-Things (IoT) devices, which are well-known for their bursty workloads and limited energy storage—usually in the form of tiny batteries. To ensure battery lifetime, dynamic voltage frequency scaling (DVFS) has become an essential technique in such SoC chips. With continuously decreasing supply level, noise margins in these devices are already being squeezed. During DVFS transition, large current that accompanies the clock speed transition runs into or out of clock networks in a few clock cycles, induces large ${\text {L}di}{/}{\mathrm {d}t}$ noise, thereby stressing the power delivery system (PDS). Due to the limited area and cost target, adding additional decoupling capacitance to mitigate such noise is usually challenging. A common approach is to gradually introduce/remove the additional clock cycles to increase/decrease the clock frequency in steps, also known as, clock skipping. However, such a technique may increase DVFS transition time, and still cannot guarantee minimal noise. In this paper, we propose a new noise-aware DVFS sequence optimization technique by formulating a mixed 0/1 programming to resolve the problems of clock skipping sequence optimization. Moreover, the method is also extended to schedule extensive wake-up activities on different clock domains for the same purpose. The experiments show that the optimized sequence is able to significantly mitigate noise within the desired transition time, thereby saving both power and energy.

Design of Power Decoupling Strategy for Single-Phase Grid-Connected Inverter Under Nonideal Power Grid

Because a single-phase inverter has a power coupling between the dc bus and the ac side, the dc bus always requires large electrolytic capacitors for the power decoupling. Although the active power decoupling circuit can restrain the ripple voltage with twice the fundamental frequency on the dc bus and reduce the required capacitance, previous research works mainly focused on the power coupling of an ideal power grid, and just decoupled the ripple power with twice the fundamental frequency. This study analyzes the power coupling in a nonideal power grid, and designs a novel decoupling method for the power with multiharmonic frequency on the dc bus. By modifying the reference values of dc series split-capacitors, the system control structure can be simplified, and the multifrequency-coupled power decoupling can be realized. Moreover, a notch filter is introduced into the dc voltage feedback path for further reducing the influence of the power coupling on the inverter output current quality. The proposed method can achieve the objective of the multifrequency-coupled power decoupling, even under a weak power-grid environment. Finally, numerical simulations and experimental results are provided to verify the effectiveness of the proposed method in comparison with the traditional capacitor decoupling framework and the dual-voltage control decoupling scheme.

A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver

Successive approximation register (SAR) analogto-digital converters (ADCs) with a charge-redistribution (CR) digital-to-analog converter (DAC) usually require a power-hungry reference driver or large decoupling capacitance, occupying significant chip area. This paper presents a CR SAR ADC with an integrated low-power and area-efficient discrete-time reference driver. An on-chip capacitor is pre-charged to the reference voltage during the tracking phase and drives the DAC of the SAR ADC passively during the conversion phase. The charge sharing between the driving capacitor and the DAC will cause reference voltage drop and code-dependent non-binary DAC switching steps. This is compensated by switching an auxiliary DAC array together with the regular binary DAC array according to each specific code. The compensation relaxes the required decoupling capacitor and introduces little overhead in power or chip area. The above-mentioned driving scheme is applied to a 10-b 20-MS/s successive approximation register (SAR) ADC fabricated in 65-nm CMOS, where the first three DAC switching steps are compensated. Moreover, redundancy is utilized to reduce the impact of reference voltage drop further. With a near-Nyquist input tone, the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of the SAR ADC with the uncompensated reference driver are 54.4 and 58.9 dB, respectively. After enabling the compensation, the SNDR and SFDR are increased to 56.8 and 72.4 dB, achieving 2.4 and 13.5 dB improvement, respectively. The SAR ADC consumes a total power of 133.1 μW while the discrete-time reference driver with and without compensation add 17.2 and 14.0 μW, respectively. The SAR ADC with integrated reference driver occupies a chip area of 0.081 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> where 8.6% is occupied by the reference driver.

Modeling and Measurement of Ground Bounce Induced by High-Speed Output Buffer With On-Chip Low-Dropout (LDO) Regulator

This study proposes a model of ground bounce induced by a high-speed output buffer with on-chip low-dropout (LDO) regulator. When the output buffer operates with a high-speed clock, high output impedance of the pass transistor and low impedance of the on-chip decoupling capacitor at load enable the ground bounce calculation by only using the self-impedance of the off-chip ground network and switching current spectra. The accuracy of the proposed model is indirectly validated by measurement. Simulated ground bounce by using the proposed model shows very good correlation with the experimentally validated SPICE model.

Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint

Integrating multiple on-chip voltage regulators in a power delivery network (PDN) can offer promising improvements in both voltage regulation and power efficiency. However, the complex interactions between active regulators and the surrounding parasitic passive network create a large number of feedback loops and thus cause stability concern for the distributed regulation network. The recently emerged PDN design methodology based on the hybrid stability theory (HST) provides a unique opportunity for taming the complex PDN stability problem. However, the HST-based stability margin is unfamiliar to circuit designers, and therefore stability-constrained design intuitions are derivable. In this brief, our systematic analysis reveals unique design considerations which can significantly impact the system-level stability and performances. Within a large design space, a comprehensive set of design studies are conducted to shed light on the tradeoffs between the HST-based stability margin and other PDN design specifications such as the quiescent current consumption, maximum switching noise, and area overhead. Useful design insights like how regulator topology, passive decoupling capacitance, and the number of on-chip regulators may be optimized for improved tradeoffs between stability and system performance are discussed. These insights can aid circuit designers to make appropriate design choices at the beginning of the design process for improved system tradeoffs.

Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators

Transient performance is one of the most crucial design properties in digital low-dropout regulator (DLDO) design. In this paper, an improved droop measurement built-in self-test (BIST) circuit for DLDOs is presented, expanding on the previous work (Dirican et al. 2018) by the same authors. The proposed BIST system can detect and store the transient droop information using droop detector and generates a digital output with a reuse based 10-bit successive-approximation (SAR) analog-to-digital converter (ADC) with better accuracy. The improvements are achieved by employing a multi-step ramp circuit and a leakage cancellation circuit. The system is made more suitable for process scaling by replacing the analog buffer with a multi-step ramp circuit. Employing a leakage cancellation circuit solves potential leakage problems during ADC operation due to the reused decoupling capacitor of the DLDO and nearly 75% reduction in maximum measurement error is observed using this feature. Additionally, the droop detector is capable of storing transient droop information with less than 0.6% error for droop voltages ranging from 45 mV to 406 mV for a nominal DLDO output voltage of 1.6 V where the supply voltage is 1.8 V. The proposed BIST circuit is designed using a 0.18 μm CMOS process in Cadence Virtuoso and verified with corner simulations.

Electrical and Thermal Co-Design for High-Power FPGA Packages

This paper describes a systematic approach to design field-programmable gate array (FPGA) package for high-power applications. As the power consumption is up to multihundred watts, not only the heat dissipation becomes a challenge, but the temperature-induced reliability concerns also mount up in the high current and noise-sensitive packages. Two most profound phenomena are substrate electromigration (EM) and package decoupling capacitor time-dependent dielectric breakdown (TDDB). The impact of EM is on maximum current-carrying capability, and impact of TDDB is on voltage noise suppression capability. However, we find both traditional static way of EM calculation and the legacy design considerations are oversimplified and insufficient for high-power products. In this paper, we report an enhanced methodology to derive substrate EM failure rate from composite current and temperature distributions. Moreover, we incorporate capacitor TDDB into the design flow to optimize capacitor lifetime for effective voltage noise suppression. In the end, we apply the electrical and thermal co-design to a 16-nm, 200-A, high-power FPGA meeting all current and dynamic noise specifications.

A Single Phase AC/DC/AC Converter With Unified Ripple Power Decoupling

In single phase ac/dc/ac converters, the low frequency ripple powers exist both at the source and load sides. Usually, large dc-link filter components are used to buffer the ripple powers, which increases volume and weight. To overcome the drawback, this paper presents a single phase ac/dc/ac current source converter with unified ripple power decoupling. The converter only consists of three bridge arms and a decoupling circuit. The three bridge arms play the role of rectification and inversion with sharing a bridge arm. And the decoupling circuit is in series with the dc-link energy storage unit to buffer the ripple powers. The circuit configuration and operation principles are introduced first. Then, a modulation strategy based on Cartesian space is developed to achieve sinusoidal input and output currents. The control idea that the dc-link current is regulated by the decoupling circuit and the averaged decoupling capacitor voltage is maintained by the rectifier is adopted. The ripple power buffer is automatically achieved. Finally, the theoretical analysis is favorably verified by the simulations and experimental results.

A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization

A two-time interleaved pipelined SAR ADC in 16-nm CMOS achieving 11.2-bit ENOB at 300 MS/s is presented. To cancel the signal-dependent voltage ripple on the reference node due to DAC switching, it employs a stabilization scheme based on the use of auxiliary DACs. The charge drawn from the reference becomes signal-independent, greatly reducing the requirements for the reference decoupling capacitance and/or buffers. The technique improves the linearity to levels better than 76-dB harmonic distortion. Power consumption is only 3.6 mW resulting in peak FoMs of 175.5 dB and 5.1 fJ/conv.step.

Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus

The superior noise reduction performance of an in-stack decoupling capacitor (DECAP) is demonstrated. A three-tier stacked demonstrator is manufactured with an ultrawide data bus that connects a top memory chip and a bottom logic chip. An in-stack evaluation circuitry on a middle tier (Si interposer) captures voltage variation waveforms during chip-to-chip data communication. In-stack DECAPs in arrays on a Si interposer and discrete ceramic capacitors on an organic interposer of a ball-grid array package are compared. Silicon measurements with an in-stack noise monitoring technique show that the DECAPs on the Si interposer more locally shunt out the AC components of power supply current over a wider frequency range than the capacitors on the package interposer.

Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint

As the clock frequency of a chip increases, the on-chip decoupling capacitor must be placed closer to the load to be effective. A method of efficiently defining the location of capacitor placement to meet specified noise limits is presented. Based on a single RL line model for the power distribution system, charging radius of the decoupling capacitor is calculated under the constraint of the target noise but not the constraint of being fully charged. Under the constraints of the length of the charging path and the target noise, discharging radius of the decoupling capacitor is figured out. The conversion coefficient that converts the radii of a decoupling capacitor in a single RL line model into the equivalent one in a meshed model is presented based on the expression that can exactly compute the impedance between any two points on an infinite meshed network. In this paper, it is shown that the conversion coefficient is a constant when the radius of the decoupling capacitor is taken as the per unit length of the meshed model.

Switched-Mode Active Decoupling Capacitor Allowing Volume Reduction of the High-Voltage DC Filters

This paper describes active shunt LC decoupling circuit with ceramic capacitors, allowing volume reduction and lifetime improvement of the high-voltage dc filters. Active filtering is based on the energy exchange between high-voltage coupling and low-voltage auxiliary capacitors. The coupling capacitor enables use of the low-voltage switched-mode power stage and low-voltage auxiliary decoupling capacitor. Advantageously, this allows to reduce power dissipation, switching frequency ripple current, and to reduce volume of the circuit. Additionally, power efficiency and capacitor lifetime are improved by using recent high-voltage coupling multilayer ceramic capacitors, reaching very low ESR. This paper provides description of the active decoupling capacitor, and shows an example of the feedback control. Obtained performances are demonstrated on the prototype of 1300-μF/450-V capacitor, allowing to reduce volume by three, when compared to ordinary 450-V electrolytic capacitor.

Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM

Design techniques for 3-D SoC stacked with a Wide I/O DRAM with through silicon via (TSV) technology were developed. Some of the developed techniques were applied to design a Wide I/O DRAM controller chip. Micro-I/O cells and area efficient decoupling capacitor cells are implemented in between the fine pitch TSV array. Test circuitry for pre-bonding TSV tests are embedded in the micro-I/O cells with small area overhead. In order to reduce ${\rm V}_{\rm min}$ degradation induced by 512 DQs simultaneous switching noise, we introduce a package-board impedance optimization scheme utilizing a full digital noise monitor. We also developed a thermal aware memory control technique to adaptively change the refresh rates per channel, which are hot due to SoC hotspots. We achieved 12.8 GB/s operation, while I/O power was reduced by 89% compared to LPDDR3.

A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique

A 12-bit 210-MS/s 2-channel time-interleaved analog-to-digital converter (ADC) employing a pipelined-SAR architecture for low-power and high-speed application is presented. The proposed ADC is partitioned into 3 stages with a passive residue transfer technique between the 1st and 2nd stages for power saving and active residue amplification between the 2nd and 3rd stages for noise consideration. Furthermore, a 2.8-bit SAR conversion embedded in the 1st stage also improves the speed and downsizes the required decoupling capacitance of reference voltage. With the foreground calibration, the inter-stage DAC error and gain/offset errors between interleaving channels are resolved. The proposed ADC, fabricated in a 65-nm CMOS technology, consumes 5.3 mW from a 1-V supply and achieves an SNDR of 63.5 dB at low input frequencies and 60.1 dB near Nyquist rate. The prototype occupies an active area of 0.48 $\text{mm}^{2}$ and the corresponding FoM is 30.3 fJ/conversion-step.

Far-End Crosstalk Noise Reduction Using Decoupling Capacitor

In this paper, a coupled miscrostrip line using the front-end decoupling capacitor is proposed to suppress the far-end crosstalk noise of the coupled microstrip line. The far-end crosstalk noise is greatly reduced from 63 to 25.7 mV. In order to further reduce the far-end crosstalk noise, a coupled microstrip line using the distributed decoupling capacitors is proposed. As compared with the coupled microstrip line using the front-end decoupling capacitor, the far-end crosstalk noise is further reduced from 25.7 mV to nearly 0 mV. In order to verify the simulation results, two coupled microstrip line circuits are fabricated and measured where the measurement results are in good agreement with the simulation results.

Control and Modulation of Bidirectional Single-Phase AC–DC Three-Phase-Leg SPWM Converters With Active Power Decoupling and Minimal Storage Capacitance

In a single-phase grid-connected nanogrid system, a bidirectional ac–dc converter is usually required to transfer energy between the ac grid and a dc bus. Active ac power balancing is often implemented to prevent the ac grid ripple power from injecting into the dc bus. A four-phase-leg sinusoidal pulsewidth-modulation (SPWM) converter can readily provide power factor correction and active ac power balancing. In this paper, the use of three-phase-leg SPWM converters for achieving these functions is analyzed. A family of bidirectional single-phase ac–dc three-phase-leg SPWM converters with an ac storage capacitor for use in a nanogrid system is designed with a general control structure and a modulation scheme for minimizing the ac storage capacitance. The general control structure is designed to achieve a decoupled system of a power-factor-correction converter cascaded with an active ac power load at the dc bus. The decoupled system is developed based on decomposition to differential-mode and common-mode voltages. The modulation method involves an extra zero-sequence voltage injection derived from the three-phase-leg SPWM voltages without introducing higher order harmonic distortions. A significant reduction of the ac storage capacitance and an improvement of converter efficiency are achieved. The design and analysis are verified by simulations and experimental measurements.

Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating

In traditional decoupling capacitor topologies, power gating can significantly degrade the system-wide power integrity of a 3-D integrated circuit since the decoupling capacitance associated with the power-gated block/plane becomes ineffective for the neighboring, active planes. Two topologies are investigated to alleviate this issue by exploiting: 1) relatively low-resistance through silicon vias (TSVs) and 2) ability of TSVs to bypass plane-level power networks when delivering the power supply voltage. In the proposed topologies, decoupling capacitors placed within a plane can provide charge to neighboring planes even when the plane is power gated, achieving up to 50% and 87% reduction in, respectively, rms power supply and power gating (in-rush current) noise at the expense of a moderate increase in physical area and peak power consumption.

Accurate IC current extraction method and power distribution network optimization

ABSTRACTObtaining correct integrated circuit (IC) current information is a key factor for power distribution network design. This letter suggests an exact IC current extraction method using a measured voltage of a board when detailed IC data cannot be accessible. Voltage waveform is measured at the closest decoupling capacitor position from an IC after the capacitor is eliminated. Using the measured voltage and new transfer function which eliminates oscilloscope probe noise effect, we are able to calculate an exact IC current. The proposed methodology is validated by comparing the simulated noise voltage with the real measured noise voltage of 1.2 V core circuit. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2175–2182, 2015

Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors

An $RLC$ model for on-chip power distribution networks (PDN) is presented for array and wire-bonded integrated circuits including interblock decoupling capacitors and C4 impedances. From the model, the supply noise produced by switching blocks as well as the impedance to ac ground as seen from any point of the circuit are calculated as a function of frequency and PDN parameters. The proposed method to perform such calculation allows optimizing relevant PDN design parameters, such as number, size, and location of supply/ground pads and location of interblock decoupling capacitors, and width and pitch of metal tracks. The PDN model and impedance calculations are validated by comparing their results with SPICE simulations, giving a maximum error of less than 1%.