Decoding Speed Research Articles

A novel BTC decoding algorithm based on the genetic algorithm in optical communication systems

Combining the advantages of both the genetic algorithm (GA) and the chase decoding algorithm, a novel improved decoding algorithm of the block turbo code (BTC) with lower computation complexity and more rapid decoding speed is proposed in order to meet the developing demands of optical communication systems. Compared with the traditional chase decoding algorithm, the computation complexity can be reduced and the decoding speed can be accelerated by applying the novel algorithm. The simulation results show that the net coding gain (NCG) of the novel BTC decoding algorithm is 1.1 dB more than that of the traditional chase decoding algorithm at the bit error rate (BER) of 10−6. Therefore, the novel decoding algorithm has better decoding correction-error performance and is suitable for the BTC in optical communication systems.

Low-latency SAO Architecture and its SIMD Optimization for HEVC Decoder

This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

Sparsity-Aware Sphere Decoding: Algorithms and Complexity Analysis

Integer least-squares problems, concerned with solving a system of equations where the components of the unknown vector are integer-valued, arise in a wide range of applications. In many scenarios the unknown vector is sparse, i.e., a large fraction of its entries are zero. Examples include applications in wireless communications, digital fingerprinting, and array-comparative genomic hybridization systems. Sphere decoding, commonly used for solving integer least-squares problems, can utilize the knowledge about sparsity of the unknown vector to perform computationally efficient search for the solution. In this paper, we formulate and analyze the sparsity-aware sphere decoding algorithm that imposes l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> -norm constraint on the admissible solution. Analytical expressions for the expected complexity of the algorithm for alphabets typical of sparse channel estimation and source allocation applications are derived and validated through extensive simulations. The results demonstrate superior performance and speed of sparsity-aware sphere decoder compared to the conventional sparsity-unaware sphere decoding algorithm. Moreover, variance of the complexity of the sparsity-aware sphere decoding algorithm for binary alphabets is derived. The search space of the proposed algorithm can be further reduced by imposing lower bounds on the value of the objective function. The algorithm is modified to allow for such a lower bounding technique and simulations illustrating efficacy of the method are presented. Performance of the algorithm is demonstrated in an application to sparse channel estimation, where it is shown that sparsity-aware sphere decoder performs close to theoretical lower limits.

Neural decoding using a parallel sequential Monte Carlo method on point processes with ensemble effect.

Sequential Monte Carlo estimation on point processes has been successfully applied to predict the movement from neural activity. However, there exist some issues along with this method such as the simplified tuning model and the high computational complexity, which may degenerate the decoding performance of motor brain machine interfaces. In this paper, we adopt a general tuning model which takes recent ensemble activity into account. The goodness-of-fit analysis demonstrates that the proposed model can predict the neuronal response more accurately than the one only depending on kinematics. A new sequential Monte Carlo algorithm based on the proposed model is constructed. The algorithm can significantly reduce the root mean square error of decoding results, which decreases 23.6% in position estimation. In addition, we accelerate the decoding speed by implementing the proposed algorithm in a massive parallel manner on GPU. The results demonstrate that the spike trains can be decoded as point process in real time even with 8000 particles or 300 neurons, which is over 10 times faster than the serial implementation. The main contribution of our work is to enable the sequential Monte Carlo algorithm with point process observation to output the movement estimation much faster and more accurately.

A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis

This paper presents a multiple code-rate turbo decoder using the reciprocal dual trellis to improve the hardware efficiency. For a convolutional code with code rate k/(k+1), its corresponding reciprocal dual code with rate 1/(k+1) has smaller codeword space than the original code while k > 1, leading to a simplified trellis of the high code-rate code. The proposed decoder architecture can decode code rate k/(k+1) constituent convolutional codes for k=1, 2, 4, 8, and 16. Moreover, two parallel soft-in/soft-out (SISO) decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.

Handwritten Chinese/Japanese Text Recognition Using Semi-Markov Conditional Random Fields

This paper proposes a method for handwritten Chinese/Japanese text (character string) recognition based on semi-Markov conditional random fields (semi-CRFs). The high-order semi-CRF model is defined on a lattice containing all possible segmentation-recognition hypotheses of a string to elegantly fuse the scores of candidate character recognition and the compatibilities of geometric and linguistic contexts by representing them in the feature functions. Based on given models of character recognition and compatibilities, the fusion parameters are optimized by minimizing the negative log-likelihood loss with a margin term on a training string sample set. A forward-backward lattice pruning algorithm is proposed to reduce the computation in training when trigram language models are used, and beam search techniques are investigated to accelerate the decoding speed. We evaluate the performance of the proposed method on unconstrained online handwritten text lines of three databases. On the test sets of databases CASIA-OLHWDB (Chinese) and TUAT Kondate (Japanese), the character level correct rates are 95.20 and 95.44 percent, and the accurate rates are 94.54 and 94.55 percent, respectively. On the test set (online handwritten texts) of ICDAR 2011 Chinese handwriting recognition competition, the proposed method outperforms the best system in competition.

비균일 양자화 방식 기반 HSS 방식의 LDPC 복호기 성능

In this paper, we presented non-uniform quantization method for LDPC decoder specified in DVB-S2 standard. There are some problems in order to implement LDPC decoder in aspect to algorithm and implementation. In algorithm aspect, because of large number of iterations, LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. Therefore, this paper studies Horizontal Shuffle Scheduling (HSS) algorithm which reduced iteration number without performance loss. In aspect of implementation, there are some solutions to improve the decoding speed, however this paper focused on non-uniform quantization which reduce the quantization bits of LDPC decoder. In simulation results, Decoding throughput of HSS LDPC decoder based on non-uniform quantization is 816Mbps and it improved 12% compared to conventional one.

Dc 분리 기반의 고속 LDPC 복호 알고리즘에 관한 연구

본 논문에서는 DVB-S2 기반 고속 LDPC 복호를 위한 알고리즘을 제안하였다. 체크 노드 연산중에 비트 노드 연산을 수행하여 기존의 LDPC 복호 알고리즘에 비해 반복횟수를 줄일 수 있는 horizontal shuffle scheduling 알고리즘을 기반으로 하여 복호 속도를 보다 고속화 할 수 있는 알고리즘을 제안하였다. 기존의 체크 노드 연산은 하나의 메모리에서 값을 가져오기 때문에 체크 노드 연산과정에서 많은 지연이 발생 하는데 이를 row weight의 개수인 dc개의 병렬구조로 설계함으로써 체크 노드 연산과정의 지연을 줄일 수 있고 따라서 고속 복호가 가능하다. 이를 DVB-S2에 제시되고 있는 다양한 부호화율에서 dc개의 분리 할 수 있는 최대의 메모리를 제시하고 전송률을 제시하였다. In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed dc-split memory structure in order to reduced the delay and high speed decoder is possible. Finally, this paper presented maximum split memory and throughput for various coding rates in DVB-S2 standard.

Flexible Multi-Core Platform for a Multiple-Format Video Decoder

This paper presents a new multi-core platform that can decode various video compression formats including MPEG-2, MPEG-4, AVS, and H.264/AVC. The developed multi-core platform consists of multiple media cores that are designed based on an application-specific instruction-set processor (ASIP). To improve the decoding speed of each media core, we developed several designated instructions that are useful for decoding various video codecs. In addition, an inter-connected hardware structure and a new synchronization algorithm are proposed to reduce inter-core communication overheads and a shared memory contention on the multi-core platform. We achieved a speed-up of 2.2× in decoding video bitstreams using several designated instructions on the media core. Furthermore, we achieved a speed-up of 5.56× in decoding video bitstreams on the multi-core platform by employing macroblock-row level parallelism, compared with the developed media core without designated instructions. The developed multi-core platform was implemented on a Xilinx Virtex5 LX330 field-programmable gate array (FPGA) that operates at 60 MHz.

Design of Encoder and Decoder for Q-Ary LDPC Codes Based on FPGA

The scheme of FPGA hardware implementation based on the RA structure of encoder for q-ary LDPC codes as well as the Max-log-BP decoding are designed emphasisly. Form the performance, speed, and resource consumption situation of coder and decoder, this scheme based on FPGA can meet the requirements of the most of communication systems.

Syntax-Based Post-Ordering for Efficient Japanese-to-English Translation

This article proposes a novel reordering method for efficient two-step Japanese-to-English statistical machine translation (SMT) that isolates reordering from SMT and solves it after lexical translation. This reordering problem, called post-ordering , is solved as an SMT problem from Head-Final English (HFE) to English. HFE is syntax-based reordered English that is very successfully used for reordering with English-to-Japanese SMT. The proposed method incorporates its advantage into the reverse direction, Japanese-to-English, and solves the post-ordering problem by accurate syntax-based SMT with target language syntax. Two-step SMT with the proposed post-ordering empirically reduces the decoding time of the accurate but slow syntax-based SMT by its good approximation using intermediate HFE. The proposed method improves the decoding speed of syntax-based SMT decoding by about six times with comparable translation accuracy in Japanese-to-English patent translation experiments.

Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format

The microprocessor industry trend towards many-core architectures introduced the necessity of devising appropriately scalable applications. While implementing software based video decoding, the main challenges are the optimized partitioning of decoder operations, efficient tracking of dependencies and resource synchronization for multiple parallel units. The same applies for hardware implementations of video decoders where monolithic approaches anticipate scalability of the design and reusability of already implemented core components.In this paper, we propose an intermediate data stream format (Meta Format Stream) which is suited for architectural decomposition of video decoding by replacing the conventional monolithic decoder architecture design with a pipelined structure. The Meta Format is forward-oriented and self contained and multistandard capable, so that processing of Meta Streams is independent of the originating bit stream. Our approach does not require special coding settings and is applicable to accelerated decoding of any standards-compliant bit stream. A H.264/AVC multiprocessing proposal is presented as a case study for the potential our our concept. The case study combines coarse grained frame-level parallel decoding of the bit stream with fine-grained macroblock level parallelism in the image processing stage.The proposed H.264 decoder achieved speedup factors of up to 7.6 on an 8 core machine with 2-way SMT. We are reporting actual decoding speeds of up to 150 frames per second in 2160p-resolution.

GPU-Based High Performance Terrain Compression

It has been well accepted that compression is essential to the real-time visualization of large-terrain elevation data. To achieve efficient performance, a terrain compression method featuring high decoding speed is proposed in this paper. A combined prediction scheme is applied in the prediction stage. Golomb-Rice coding is then used to encode the residuals after the prediction stage. The style of the codeword is tailored to make the decoding process amenable to a GPU implementation. Then batching is used to further improve the decoding speed. The proposed method is easy to implement and simple to integrate into existing systems. Experiments show that the compression rate is better than PNG. In terms of decompression efficiency, this method archives a decoding speed of over 5.8 Gpix/s, which is much faster than most existing systems.

Algebraic decoding of the binary systematic (71, 36, 11) quadratic residue code

A fast and efficient algebraic decoding algorithm (ADA) is proposed to correct up to five possible error patterns in the binary systematic (71, 36, 11) quadratic residue (QR) code. The technique required here is based on the ADA developed by He et al. [2001. Decoding the (47, 24, 11) quadratic residue code. IEEE transactions on information theory, 47 (3), 1181–1186.] and the modification of the ADA developed by Lin et al. [2010. Decoding of the (31, 16, 7) quadratic residue code. Journal of the Chinese institute of engineers, 33 (4), 573–580; 2010. High speed decoding of the binary (47, 24, 11) quadratic residue code. Information sciences, 180 (20), 4060–4068]. The new proposed conditions and the error-locator polynomials for different numbers of errors in the received word are derived. Simulation results show that the decoding speed of the proposed ADA is faster than the other existing ADAs.

멀티미디어 기반 해상통신을 위한 DVB-S2 기반 고속 LDPC 복호를 위한 알고리즘에 관한 연구

본 논문에서는 멀티미디어 기반의 해상통신을 위한 DVB-S2 기반 고속 LDPC 복호를 위한 알고리즘을 제안하였다. 체크 노드 연산중에 비트 노드 연산을 수행하여 기존의 LDPC 복호 알고리즘에 비해 반복횟수를 줄일 수 있는 horizontal shuffle scheduling 알고리즘을 기반으로 하여 복호 속도를 보다 고속화 할 수 있는 알고리즘을 제안하였다. 기존의 체크 노드 연산은 하나의 메모리에서 값을 가져오기 때문에 체크 노드 연산과정에서 많은 지연이 발생하는데 이를 dc개의 병렬구조로 설계함으로써 체크 노드 연산과정의 지연을 줄일 수 있고 따라서 고속 복호가 가능하다. 이를 시뮬레이션 한 결과, 최대 반복 30회를 수행하였을 때 HSS 알고리즘은 326 Mbit/s, 제안한 알고리즘은 2.29 Gbit/s로 약 7배 이상의 복호 throughput을 얻을 수 있었다. In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.

HSS 기반 초고속 LDPC 복호를 위한 구조

본 논문은 위성방송 전송 규격인 DVB-S2의 기반 채널 부호로 사용되는 LDPC를 고속 복호를 위해 HSS(Horizontal Shuffle Scheduling) 방식을 기반으로 고속 복호기 구조를 연구하였다. 첫째로 HSS방식에서 발생하는 메모리 충돌을 극복하는 방식을 제시한다. 둘째로 고속 복호를 위해 LUT(Look Up Table)을 이용하는 Sum-Product 알로리즘 대신 min값에서 scaling factor를 곱하는 Normalized Min-Sum 알고리즘을 사용하였으며, 성능 향상을 위해 check node에서 bit node로 입력되는 값의 부호를 확인하여 신뢰성 없는 값을 삭제하는 Self-Correct 방식을 제시하여 sum-product 방식에서 발생하는 bottle neck 현상을 하였다. 마지막으로 고속화를 위한 효율적인 메모리 구조를 제안한다. This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc<TEX>${\rightarrow}$</TEX>v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'<TEX>${\rightarrow}$</TEX>c and the sign of the previous incoming messages Moldv'<TEX>${\rightarrow}$</TEX>c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

3D range geometry video compression with the H.264 codec

Advances in three-dimensional (3D) scanning have enabled the real-time capture of high-resolution 3D videos. With these advances brings the challenge of streaming and storing 3D videos in a manner that can be quickly and effectively used. This research addresses this challenge by generalizing the Holovideo technique to video codecs that use the YUV color space such as the H.264 codec. With the H.264 codec, we have achieved a compression ratio of over 6086:1 (Holovideo to OBJ) with a reasonably high quality; utilizing an NVIDIA GeForce 9400m GPU, we have realized 17 frames per second encoding, and 28 frames per second decoding speed, making it a viable solution for real-time 3D video compression.

Context Adaptive Variable Length Decoding Optimization and Implementation on Tms320c64 Dsp for H.264/Avc

Context Adaptive Variable Length Decoding (CAVLD) module takes the lion chair of the H.264/AVC video decoder time due to its complexity. In order to ameliorate decoding speed, a new CAVLD algorithm and an efficient internal memory design were implemented on Digital Signal Processor (DSP). The proposed CAVLD algorithm, Zero Length Prefix (ZLP), was designed to optimize the first syntax element: the CoeffToken. ZLP implementation reduces CAVLD execution time to 21% instead of 41% from decoding time with a throughput of 1.28 MegaMB/s. In addition, the decoder speed was increased from 36 frames per second (fps) to 44 fps for a CIF compressed bitstream.

움직임 정보 피드백이 가능한 응용을 위한 BER모델을 이용한 고속 분산 비디오 복호화 기법

DVC (Distributed Video Coding) techniques need feedback channel for parity bit control to achieve the good RD performances, however, this causes the DVC system to have high decoding latency. In order to implement in real time environments and to accelerate commercializations, many research works have been focusing on the development of fast video decoding algorithm. As one of the real time implementations, this paper deals with a novel DVC scheme suitable for some application areas where source statistics such as motion information can be provided to the encoder side from the decoder side. That is, this paper propose a fast distributed video decoding scheme to improve the decoding speed by using the feedback of motion information derived in SI generation. Through computer simulations, it is shown that the proposed method outperforms the conventional fast DVC decoding schemes.

A pipelined 8-bit soft decision viterbi decoder for IEEE802.11ac WLAN systems

Recently, IEEE802.11ac, which can support ultra high speed data communications up to 1Gbps with low power consumption, has been drawing much attention in the consumer electronic field. In the IEEE802.11ac system, one of the critical implementation issues is to find the optimum architecture of demodulator satisfying the speed requirement. A Viterbi decoder is an essential part for error correction in the demodulator and has a design problem with respect to hardware costs as well as decoding speed. Among various functional blocks in the Viterbi decoder, both hardware complexity and decoding speed highly depend on the architecture of ACS. Because of a feed-back structure, it is very difficult for the ACS to perform its task at a high data rate at low power. Substantial previous works have been presented in order to enhance the decoding speed or to reduce the hardware costs. However, the approaches are insufficient to meet the high-speed and low-cost requirements of a high-level soft decision (up to 8 bits) Viterbi decoder for IEEE802.11ac systems. In this paper, therefore, we propose a cost-efficient high-level soft decision Viterbi decoder with a multi-stage pipelined ACS for IEEE802.11ac systems. From the implementation and verification results under 0.13μm CMOS technology, we find that the proposed architecture can meet the required data rate of IEEE802.11ac and reduce the hardware complexity by about 70% and 90% compared with conventional single-stage pipelined ACS and look-ahead ACS structures, respectively.