Power Consumption Of Decoder Research Articles

Error Control Coding in Low-Power Wireless Sensor Networks: When Is ECC Energy-Efficient?

This paper examines error control coding (ECC) use in wireless sensor networks (WSNs) to determine the energy efficiency of specific ECC implementations in WSNs. ECC provides coding gain, resulting in transmitter energy savings, at the cost of added decoder power consumption. This paper derives an expression for the critical distance dCR, the distance at which the decoder's energy consumption per bit equals the transmit energy savings per bit due to coding gain, compared to an uncoded system. Results for several decoder implementations, both analog and digital, are presented for dCR in different environments over a wide frequency range. In free space, dCR is very large at lower frequencies, suitable only for widely spaced outdoor sensors. In crowded environments and office buildings, dCR drops significantly, to 3 m or greater at 10 GHz. Interference is not considered; it would lower dCR. Analog decoders areshown to be the mostenergy-efficient decoders in this study.

A low power turbo/Viterbi decoder for 3GPP2 applications

This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-/spl mu/m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.

A very low-complexity space-time block decoder (STBD) ASIC for wireless systems

This paper presents a computationally efficient application-specific integrated circuit (ASIC) implementation for the decoding of space-time block codes (STBCs) . Alternative methods of evaluating the originally proposed maximum-likelihood decision metrics are explored at the algorithm and architectural level. At the algorithm level, unique decoding techniques are developed that result in computation savings of as much as 65%. At the architectural level, a low-computation symmetrical approach for the implementation of the proposed algorithm is presented. The proposed ASIC architecture offers considerable computation reductions leading to substantial power and area savings compared to a direct implementation of the original algorithm. The proposed architecture was realized in an ASIC referred to as the ST block decoder ASIC. The chip was fabricated using 0.18-/spl mu/m CMOS technology and occupies a core area of 0.25 mm/sup 2/. The ASIC architecture is highly scalable and can implement 2 /spl times/ 2, 8 /spl times/ 3, and 8 /spl times/ 4 STBCs with modulation formats ranging from binary-phase shift keying (BPSK) to 16 quadrature amplitude modulation (QAM), and can operate at any symbol rate up to 20 Mbaud. Depending on the mode of operation, the decoder power consumption ranges from 0.54 mW for 2 /spl times/ 2 BPSK systems to 1.89 mW for 8 /spl times/ 4 16-QAM systems.

A reconfigurable, power-efficient adaptive Viterbi decoder

Error-correcting convolutional codes provide a proven mechanism to limit the effects of noise in digital data transmission. Although hardware implementations of decoding algorithms, such as the Viterbi algorithm, have shown good noise tolerance for error-correcting codes, these implementations require an exponential increase in very large scale integration area and power consumption to achieve increased decoding accuracy. To achieve reduced decoder power consumption, we have examined and implemented decoders based on the reduced-complexity adaptive Viterbi algorithm (AVA). Run-time dynamic reconfiguration is performed in response to varying communication channel-noise conditions to match minimized power consumption to required error-correction capabilities. Experimental calculations indicate that the use of dynamic reconfiguration leads to a 69% reduction in decoder power consumption over a nonreconfigurable field-programmable gate array implementation with no loss of decode accuracy.

Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage

Turbo-code becomes popular for the next generation wireless communication systems because of its remarkable coding performance. One of the problems for decoding turbo-code in the receiver is the complexity and the high power consumption since multiple iterations of Soft Output Viterbi Algorithm (SOVA) or Maximum a posteriori (MAP) decoding have to be carried out to decode a data frame. To reduce the complexity of the turbo-code decoder, adaptive iteration based on cyclic redundancy checking (CRC) and output convergence approaches has been proposed to reduce the average number of iterations required for decoding a data frame. This results in a system that has variable workload since the amount of computation required for decoding each data frame is different. In this work, we propose a dynamic voltage scaling approach to further reduce the power consumption. Different from other variable workload systems, the workload here is not known at the time when the data is being decoded. Thus, optimum voltage assignment is not feasible. We propose several heuristic algorithms to assign supply voltage for different decoding iterations. Simulation results show that significant reduction of power consumption is achieved comparing with the system using fixed supply voltage.

Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications

Channel coding is commonly incorporated to obtain sufficient reception quality in wireless mobile communications transceiver to counter channel degradation due to intersymbol interference, multipath dispersion, and thermal noise induced by electronic circuit devices. For low energy mobile wireless communications, it is highly desirable to incorporate a decoder which has a very low power consumption while achieving a high coding gain. In this paper, a sub-optimal low-complexity multi-stage pipeline decoder architecture for a powerful channel coding technique known as “turbo-code” is presented. The presented architecture avoids complex operations such as exponent and logarithmic computations. The turbo-code decoding algorithm is reformulated for an efficient VLSI implementation. Furthermore, the communication channel statistic estimation process has been completely eliminated. The architecture has been designed and implemented with the 0.6 μm CMOS standard cell technology using Epoch computer aided design tool. The performance and the circuit complexity of the turbo-code decoder are evaluated and compared with the other types of well-known decoders. The power consumption of the low-complexity turbo-code decoder is comparable to that of the conventional convolutional-code decoder. However, the low-complexity turbo-code decoder has a significant coding gain over the conventional convolutional-code decoders and it is well suited for very low power applications.

An error bound for reduced-state Viterbi decoding of TCM codes

An upper bound is given on the error event rate of reduced-state Viterbi decoding of trellis-coded modulation (TCM) codes. Such reduced-state decoding could form the heart of an adaptive-complexity approach that saves substantially on required decoding power consumption, an important consideration in handheld portable communications. The bound is based on a difference-state formulation utilizing the uniform error properties of the codes. It fully includes the effect of finite decoding depth L, and is efficiently computed with a single forward pass through the encoder trellis.