Decoder Hardware Architecture Research Articles

Decoder-in-the-Loop: Genetic Optimization-Based LDPC Code Design

LDPC code design tools typically rely on asymptotic code behavior and are affected by an unavoidable performance degradation due to model imperfections in the short length regime. We propose an LDPC code design scheme based on an evolutionary algorithm, the Genetic Algorithm (GenAlg), implementing a "decoder-in-the-loop" concept. It inherently takes into consideration the channel, code length and the number of iterations while optimizing the error-rate of the actual decoder hardware architecture. We construct short length LDPC codes (i.e., the parity-check matrix) with error-rate performance comparable to, or even outperforming that of well-designed standardized short length LDPC codes over both AWGN and Rayleigh fading channels. Our proposed algorithm can be used to design LDPC codes with special graph structures (e.g., accumulator-based codes) to facilitate the encoding step, or to satisfy any other practical requirement. Moreover, GenAlg can be used to design LDPC codes with the aim of reducing decoding latency and complexity, leading to coding gains of up to $0.325$ dB and $0.8$ dB at BLER of $10^{-5}$ for both AWGN and Rayleigh fading channels, respectively, when compared to state-of-the-art short LDPC codes. Also, we analyze what can be learned from the resulting codes and, as such, the GenAlg particularly highlights design paradigms of short length LDPC codes (e.g., codes with degree-1 variable nodes obtain very good results).

An Architecture for Asymmetric Numeral Systems Entropy Decoder - A Comparison with a Canonical Huffman Decoder

This paper proposes two decoder hardware architectures for the tabled asymmetric numeral systems (tANS) compression algorithm, a software implementation of which is used by Apple and Facebook due to its efficiency. To the best of our knowledge, hardware architectures for the highly efficient tANs algorithm are investigated by the authors so far uniquely. The tANS decoder hardware architectures have been compared to a novel Huffman decoder hardware architecture because the Huffman coding is known as one of the fastest coding techniques in hardware and software. For the proposed architectures, the decoding throughput is highly dependent on the compression ratio of data. Experimental results show that the proposed tANS architecture outperforms the tANS software decoder and can achieve the throughput up to 200MB/s using current FPGA technology. Compared to canonical Huffman decoder the proposed hardware architecture provides up to four times higher decoding throughput.

Where to go from here? New cross layer techniques for LTE Turbo-Code decoding at high code rates

Abstract. The wide range of code rates and code block sizes supported by todays wireless communication standards, together with the requirement for a throughput in the order of Gbps, necessitates sophisticated and highly parallel channel decoder architectures. Code rates specified in the LTE standard, which uses Turbo-Codes, range up to r=0.94 to maximize the information throughput by transmitting only a minimum amount of parity information, which negatively impacts the error correcting performance. This especially holds for highly parallel hardware architectures. Therefore, the error correcting performance must be traded-off against the degree of parallel processing. State-of-the-art Turbo-Code decoder hardware architectures are optimized on code block level to alleviate this trade-off. In this paper, we follow a cross-layer approach by combining system level knowledge about the rate-matching and the transport block structure in LTE with the bit-level technique of on-the-fly CRC calculation. Thereby, our proposed Turbo-Code decoder hardware architecture achieves coding gains of 0.4–1.8 dB compared to state-of-the-art accross a wide range of code block sizes. For the fully LTE compatible Turbo-Code decoder, we demonstrate a negligible hardware overhead and a resulting high area and energy efficiency and give post place and route synthesis numbers.

Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

Motivated by the importance of hardware implementation in practical turbo decoders, a simplified, yet effective, <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$n$</tex></formula> -input <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\max^{\ast}$</tex> </formula> approximation algorithm is proposed with the aim being its efficient implementation for very low-complexity turbo decoder hardware architectures. The simplification is obtained using an appropriate digital circuit for finding the first two maximum values in a set of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$n$</tex></formula> data that embeds the computation of a correction term. Various implementation results show that the proposed architecture is simpler by 30%, on average, than the constant logarithmic-maximum a posteriori (Log-MAP) one, in terms of chip area with the same delay. This comes at the expense of very small performance degradation, in the order of 0.1 dB for up to moderate bit error rates, e.g., <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$10^{-5}$</tex></formula> , assuming binary turbo codes. However, when applying scaling to the extrinsic information, the proposed algorithm achieves almost identical Log-MAP turbo code performance for both binary and double-binary turbo codes, without increasing noticeably the implementation complexity.

Systematic analysis of the decoding delay in multiview video

We present a framework for the analysis of the decoding delay in multiview video coding (MVC). We show that in real-time applications, an accurate estimation of the decoding delay is essential to achieve a minimum communication latency. As opposed to single-view codecs, the complexity of the multiview prediction structure and the parallel decoding of several views requires a systematic analysis of this decoding delay, which we solve using graph theory and a model of the decoder hardware architecture. Our framework assumes a decoder implementation in general purpose multi-core processors with multi-threading capabilities. For this hardware model, we show that frame processing times depend on the computational load of the decoder and we provide an iterative algorithm to compute jointly frame processing times and decoding delay. Finally, we show that decoding delay analysis can be applied to design decoders with the objective of minimizing the communication latency of the MVC system.

Quasi-Cyclic LDPC Codes for the Magnetic Recording Channel: Code Design and VLSI Implementation

By implementing a field-programmable gate array (FPGA)-based simulator, we investigate the performance of randomly constructed high-rate quasi-cyclic (QC) low-density parity-check (LDPC) codes for the magnetic recording channel at very low block sector error rates. On the basis of extensive simulations, we conjecture guidelines for designing randomly constructed high-rate regular QC-LDPC codes with low error floor for the magnetic recording channel. Experimental results show that our high-rate regular QC-LDPC codes do not suffer from error floor, at least at block error rates of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> , and can realize significant coding gains over Reed-Solomon codes that are used in current practice. Furthermore, we develop a QC-LDPC decoder hardware architecture that is well suited to achieving high decoding throughput. Finally, to evaluate the implementation feasibility of LDPC codes for the magnetic recording channel, using 0.13 mum standard cell and memory libraries, we designed a read channel signal processing datapath consisting of a parallel max-log-MAP detector and a QC-LDPC decoder, which can achieve a throughput up to 1.8 Gb/s

MPEG-2 video decoder for the digital HDTV Grand Alliance system

A real-time video decoder which can decompress an MPEG-2 video bitstream having a bitrate up to 45 Mb/s is described. The decoder, which can operate at HDTV pixel rates, was built as part of the Grand Alliance (GA) HDTV system. It is currently undergoing testing by the Advisory Committee on Advanced Television Service (ACATS). The hardware converts encoded bitstreams into displayable video signals. Various video and film frame rates are supported, and switching between all format and frame rate combinations is accomplished seamlessly. This paper describes the GA video decoder hardware architecture and implementation. >

Grand alliance MPEG‐2‐based video decoder with parallel processing architecture

AbstractA practical and unique hardware architecture for video bitstream source decoding and video postprocessing of a Moving Pictures Expert Group (MPEG‐2)‐based high‐definition television (HDTV) compressed bitstream has been implemented to impose minimal limitations on the video source coding algorithm. The Grand Alliance (GA) MPEG‐2‐based HDTV codec achieves a high degree of source and channel coding efficiency while preserving the delivery of high‐resoultion picture quality in a variety of video input and output formats in bandwidth‐limited channels. The video source decoder hardware architecture necessary to achieve the data decoding and ensuing video postprocessing poses numerous technologic challenges to the system designer, who must tradeoff minimizing codec constraints with the eventual commercialization of a video decoder for a consumer television receiver product. The powerful and flexible coding algorithm necessary to satisfy the HDTV picture quality and transmission channel bandwidth limitation requirements results in an encoder‐output bitstream that necessitates high throughout decoding. Although the transmitted bitstream is of constant rate due to rate buffering, bistreams internal to the codec are both peaky and bursty. An intelligent distributive parallel processing decoding architecture has been developed to dynamically partition the MPEG‐2 bitstream into a number of decodable subset bitstreams, while placing minimal constraints on the encoding algorithm. This architecture allows for high‐speed, efficient decoding of the bitstream, and can be a prelude to the development of a cost‐effective consumer product. Further architecture refinements can be explored, including implementation in VLSI.