Decision Feedback Equalizer Receiver Research Articles

Transceiver Optimization for Two-Hop AF MIMO Relay Systems With DFE Receiver and Direct Link

In this paper, we consider precoding and receiving matrices optimization for a two-hop amplify-and-forward (AF) multiple-input multiple-output (MIMO) relay system with a decision feedback equalizer (DFE) at the destination node in the presence of the direct source-destination link. By adopting the minimum mean-squared error (MMSE) criterion, we develop two new transceiver design algorithms for such a system. The first one employs an iterative procedure to design the source, relay, feed-forward, and feedback matrices. The second algorithm is a non-iterative suboptimal approach which decomposes the optimization problem into two tractable subproblems and obtains the source and relay precoding matrices by solving the two subproblems sequentially. Simulation results validate the better MSE and bit-error-rate (BER) performance of the proposed algorithms and show that the non-iterative suboptimal method has a negligible performance loss when the ratio of the source node transmission power to the relay node transmission power is small. In addition, the computational complexity analysis suggests that the second algorithm and one iteration of the first algorithm have the same order of complexity. As the first algorithm typically converges within a few iterations, both proposed algorithms exhibit a low complexity order.

Current-integrating summer for DFE receiver with low common mode variation

This paper presents the design of current integrating based decision feedback equalizer (DFE) receiver. The proposed DFE incorporates a folded topology of current integrating summer which has reduced common mode voltage drop and variation at the summing nodes compared to existing topologies. The DFE uses a half-rate, soft decision architecture to alleviate the timing constraint of first feedback tap. Further, direct feedback architecture and reduced supply voltage are employed to reduce the power consumption. The DFE receiver has been implemented in 65 nm CMOS technology and operates at a data rate of 8 Gb/s over an 18.5 inch FR4 channel which has a loss of about 12.4 dB at 4 GHz frequency. It draws a current of 3.89 mA from a 0.9 V supply consuming a power of 3.5 mW.

A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces

This brief presents a phase-difference modulation signaling enhanced by decision feedback equalization for multi-drop memory interfaces. The phase-difference modulation signaling enables efficient data communication via a multi-drop channel, but only if the stub lengths are specially engineered. In this brief, the phase-difference modulation signaling is combined with decision feedback equalization to extend the applicable channel range. A test chip with a phase-difference-modulation transmitter and a decision feedback equalization receiver was fabricated in 65-nm CMOS technology. With a 2-tap decision feedback equalization, the test chip achieved the data rate of 7.8 Gb/s/pin via the both multi-drop channels with a long 10-cm stub and a short 2-cm stub, whereas the previous work without decision feedback equalization does not work with the 2-cm stub channel at 7.8Gb/s/pin.

A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS

Rapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this article, we present a baud-rate ROO receiver that can turn on in just 10 ns (~120 UI). Baud-rate clock and data recovery (CDR) is implemented using a new timing function that is amenable to operation with a loop un-rolled decision feedback equalizer (DFE). The receiver is turned on rapidly by sweeping the recovered clock phase across the received data bit by offsetting the digitally controlled oscillator (DCO) frequency at each power-ON event. This first ROO DFE receiver also includes a continuous-time linear equalizer (CTLE) and three-tap DFE to compensate up to 20-dB channel loss at Nyquist. Fabricated in a 65-nm CMOS process, the prototype receiver recovers 12 Gb/s with BER 30-MHz JTOL corner, 377 $fs_{\text {rms}}$ recovered clock jitter, and 3.8-pJ/bit energy efficiency.

Lower Bounds and Approximations for the Information Rate of the ISI Channel

We consider the discrete-time intersymbol interference (ISI) channel model, with additive Gaussian noise and fixed independent identically distributed inputs. In this setting, we investigate the expression put forth by Shamai and Laroia as a conjectured lower bound for the input–output mutual information after application of a minimum mean-square error decision-feedback equalizer receiver. A low-signal to noise ratio (SNR) expansion is used to prove that the conjectured bound does not hold under general conditions, and to characterize inputs for which it is particularly ill-suited. One such input is used to construct a counterexample, indicating that the Shamai–Laroia expression does not always bound even the achievable rate of the channel, thus excluding a natural relaxation of the original conjectured bound. However, this relaxed bound is then shown to hold for any finite entropy input and ISI channel, when the SNR is sufficiently high. We derive two conditions under which the relaxed bound holds, involving compound channel capacity and quasiconvexity arguments. Finally, new simple bounds for the achievable rate are proven, and compared with other known bounds. Information-estimation relations and estimation–theoretic bounds play a key role in establishing our results.

Precoding Techniques for MIMO AF Relaying Systems With Decision Feedback Receiver

In this paper, we provide new precoding schemes which jointly optimize the source and relay precoders in multiple-input multiple-output amplify-and-forward relaying systems with minimum mean-squared error decision feedback equalizer (DFE) at the destination node. Instead of conventional schemes which resort to an iterative method, we propose simple precoding schemes based on a closed-form solution. To this end, we first extend the decomposable property of the error covariance matrix for a linear receiver to relaying systems with DFE receivers. Then, we suggest two closed-form solutions which successively identify the source and the relay precoders. To improve the performance, a mode selection which adaptively chooses one of the two closed-form precoding schemes according to the channel conditions is introduced. Then, we propose a simple eigenvalue based mode selection algorithm, and analyze its selection probability behavior for Rayleigh fading channels. Simulation results demonstrate that the performance of the proposed method is almost identical to the iterative solution with much reduced complexity.

A wide band QAM receiver based on DFE to reject ISI in wireless time varying fading channel

Quadrature Amplitude Modulation (QAM) system with high data rate suffers from Inter-Symbol-Interference (ISI) in frequency-selective wireless channel. To reduce this ISI signal, Decision Feedback Equalizer (DFE) is used. When the channel impulse response is time varying, the channel's coefficients need to be adaptively estimated. Adaptive implementation of the forward filter on the conventional DFE can track the time variation of the channel coefficients, but its tracking capability depends on the covariance matrix of the receiver vector and the speed of channel variation. In this paper, wide band QAM receiver is proposed with new arrangement of the DFE filters. Data diversity at the receiver is achieved by using N antennas at its input. The forward filter of the DFE will be used as a Maximum-Ratio-Combiner (MRC) as well as a channel compensator. By first removing the ISI signal from the received vector, the tracking performance of the forward filter will be enhanced. The new performance of the proposed receiver will be compared with the conventional DFE receiver. The tracking performance of the forward filter using LMS and RLS algorithms in the new arrangement is compared with that of the conventional DFE receiver.

A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE

A low-power receiver with a one-tap data and edge decision-feedback equalizer (DFE) and a clock recovery circuit is presented. The receiver employs analog adders for the tap-weight summation in both the data and the edge path to simultaneously optimize both the voltage and timing margins. A switched-capacitor input stage allows the receiver to be fully compatible with near-GND input levels without extra level conversion circuits. Furthermore, the critical path of the DFE is simplified to relax the timing margin. Fabricated in the 65-nm CMOS technology, a prototype DFE receiver shows that the data-path DFE extends the voltage and timing margins from 40 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> and 0.3 unit interval (UI), respectively, to 70 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> and 0.6 UI, respectively. Likewise, the edge-path equalizer reduces the uncertain sampling region (the edge region), which results in 17% reduction of the recovered clock jitter. The DFE core, including adders and samplers, consumes 1.1 mW from a 1.2-V supply while operating at 6.4 Gb/s.

A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm

This paper presents a low-power decision-feedback equalizer (DFE) receiver front-end and a two-step minimum bit-error-rate (BER) adaptation algorithm. A high energy efficiency of 0.46 mW/Gbps is made possible by the combination of a direct-feedback finite-impulse-response (FIR) DFE, an infinite-impulse-response (IIR) DFE, and a clock-and-data recovery (CDR) circuit with adjustable timing offsets. Based on this architecture, the power-hungry stages used in prior DFE receivers such as the continuous-time linear equalizer (CTLE), the current-mode summing circuit for a multitap DFE, and the fast selection logic for a loop-unrolling DFE can all be removed. A two-step adaptation algorithm that finds the equalizer coefficients minimizing the BER is described. First, an extra data sampler with adjustable voltage and timing offsets measures the single-bit response (SBR) of the channel and coarsely tunes the initial coefficient values in the foreground. Next, the same circuit measures the eye-opening and bit-error rates and fine tunes the coefficients in background using a stochastic hill-climbing algorithm. A prototype DFE receiver fabricated in a 65-nm LP/RF CMOS dissipates 2.3 mW and demonstrates measured eye-opening values of 174 mV pp and 0.66 UIpp while operating at 5 Gb/s with a -15-dB loss channel.

A DFE Receiver With Equalized VREF for Multidrop Single-Ended Signaling

In this brief, decision-feedback equalization (DFE) receiver for multidrop single-ended signaling is described. The proposed DFE receiver adopts a reference voltage having equalization information to remove channel intersymbol interference. It uses a smaller number of DFE tap elements than the conventional DFE receiver for the same level of equalization, resulting in reduced power consumption and silicon area, particularly for multi-input/output interface. The proposed DFE receiver was fabricated in a 0.13- μm CMOS process, whose evaluation results indicate a reliable operation up to 3.40-Gb/s data rate with reduced power consumption.

A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation

This paper presents a low-power receiver with two-tap decision feedback equalization (DFE) and novel far-end crosstalk (FEXT) cancellation capability, implemented in a 45-nm SOI CMOS process. The receiver employs a half-rate speculative DFE architecture to allow for the use of low-power front-end circuitry and CMOS clock buffers. In the proposed architecture, a switched-capacitor sample-hold at the front-end is employed to perform DFE tap summation. This technique is generalized to implement n taps of equalization. The receiver compensates the effect of crosstalk without making a decision on the received aggressor signal. Due to the low-power nature of the switched-capacitor front-end, the crosstalk cancellation is possible with only 33 μW/Gbps/lane power overhead. The receiver was tested over channels with different levels of loss and coupling. The signaling rate with BER <; 10-12 was significantly increased with the use of DFE and crosstalk cancellation scheme for highly coupled and lossy PCB traces. The DFE receiver equalizes 15-Gb/s data over a channel with more than 14-dB loss while consuming about 7.5 mW from a 1.2-V supply. At lower data rates it equalizes channels with over 21-dB loss.

Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links

This paper investigates the performance benefit of using nonuniformly quantized ADCs for implementing high-speed serial receivers with decision-feedback equalization (DFE). A way of determining an optimal set of ADC thresholds to achieve the minimum bit-error rate (BER) is described, which can yield a very different set from the one that minimizes signal quantization errors. By recognizing that both the loop-unrolling DFE receiver and ADC-based DFE receiver decide each received bit based upon the result of a single slicer, an efficient architecture named reduced-slicer partial-response DFE (RS-PRDFE) receiver is proposed. The RS-PRDFE receiver eliminates redundant or unused slicers from the previous DFE receiver implementations. Both the simulation and measurement results from a 10 Gb/s ADC-based receiver fabricated in 65 nm CMOS technology and multiple backplane channels demonstrate that the RS-PRDFE can achieve the BER of a 3-4-bit uniform ADC only with 4 data slicers. Also, the combined use of linear equalizers (LEs) can further reduce the required slicer count in RS-PRDFE receivers, but only when the LEs are realized in analog domain.

A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling

A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25- mum CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation was implemented by switching the capacitance values of the two output nodes of a differential integrator, depending on the previous decision data. A look-ahead scheme was used to reduce the DFE loop delay. A MUX-embedded D flip-flop was used in the look-ahead circuit to further reduce the DFE loop delay and latency. The DFE operation enhanced the voltage margins by 110% and 90% at the 2-Gb/s stubless channel and the 1.2-Gb/s stub series terminated logic channel, respectively. The chip area and the power dissipation of the proposed receiver chip were 220 times 120 mum2 and 10 mW, respectively, at the data rate of 2 Gb/s.

Advanced Receiver Design for Quadrature OFDMA Systems

Quadrature orthogonal frequency division multiple access (Q-OFDMA) systems have been recently proposed to reduce the peak-to-average power ratio (PAPR) and complexity, and improve carrier frequency offset (CFO) robustness and frequency diversity for the conventional OFDMA systems. However, Q-OFDMA receiver obtains frequency diversity at the cost of noise enhancement, which results in Q-OFDMA systems achieving better performance than OFDMA only in the higher signal-to-noise ratio (SNR) range. In this paper, we investigate various detection techniques such as linear zero forcing (ZF) equalization, minimum mean square error (MMSE) equalization, decision feedback equalization (DFE), and turbo joint channel estimation and detection, for Q-OFDMA systems to mitigate the noise enhancement effect and improve the bit error ratio (BER) performance. It is shown that advanced detections, for example, DFE and turbo receiver, can significantly improve the performance of Q-OFDMA.

Bluetooth Receiver Design Based on Laurent's Decomposition

In this paper, we present a receiver design for Bluetooth transmission based on Laurent's decomposition of the Bluetooth transmit signal. The main features of this receiver are 1) its low complexity compared to alternative solutions; 2) its excellent performance close to the theoretical limit; and 3) its high robustness against frequency offsets, phase noise, and modulation index variations, which are characteristic for low-cost Bluetooth devices. In particular, we show that the devised noncoherent decision-feedback equalization receiver achieves a similar performance as a recently proposed two-state noncoherent sequence detector, while it is advantageous in terms of complexity. The new receiver design is therefore highly attractive for a practical implementation.

CCK Demodulation via Symbol Decision Feedback Equalizer

A symbol decision feedback equalization (DFE) technique is developed for demodulating complementary code keying (CCK) signals. The efficacy of the proposed receiver is demonstrated on the physical layer (PHY) specified in the IEEE 802.11b wireless local area network (WLAN) standard. Packet error rate (PER) performance is compared with that of the conventional RAKE receiver. The proposed receiver structure and its low complexity variations demonstrate significant performance advantages over the RAKE receiver, especially in severe multipath channels. While a large delay spread can limit the performance of two low-complexity variations discussed here, performance of the optimal symbol DFE receiver is not limited by delay spread as long as the channel signal-to-noise ratio (SNR) is sufficiently high.

Bounding performance and suppressing intercarrier interference in wireless mobile OFDM

While rapid variations of the fading channel cause intercarrier interference (ICI) in orthogonal frequency-division multiplexing (OFDM), thereby degrading its performance considerably, they also introduce temporal diversity, which can be exploited to improve performance. We first derive a matched-filter bound (MFB) for OFDM transmissions over doubly selective Rayleigh fading channels, which benchmarks the best possible performance if ICI is completely canceled without noise enhancement. We then derive universal performance bounds which show that the time-varying channel causes most of the symbol energy to be distributed over a few subcarriers, and that the ICI power on a subcarrier mainly comes from several neighboring subcarriers. Based on this fact, we develop low-complexity minimum mean-square error (MMSE) and decision-feedback equalizer (DFE) receivers for ICI suppression. Simulations show that the DFE receiver can collect significant gains of ICI-impaired OFDM with affordable complexity. In the relatively low Doppler frequency region, the bit-error rate of the DFE receiver is close to the MFB.

A robust adaptive DFE receiver for DS-CDMA systems under multipath fading channels

This paper presents a novel receiver design from signal processing viewpoint for direct-sequence code-division multiple access (DS-CDMA) systems under multipath fading channels. A robust adaptive decision-feedback equalizer (DFE) is developed by using optimal filtering technique via minimizing the mean-square error (MSE). The multipath fading channels are modeled as tapped-delay-line filters, and the tap coefficients are described as Rayleigh distributions in order to imitate the frequency-selective fading channel. Then, a robust Kalman filtering algorithm is used to estimate the channel responses for the adaptation of the proposed DFE receiver under the situation of partially known channel statistics. The feedforward and feedback filters are designed by using not only the estimated channel responses but the uncertainties and error covariance of channel estimation as well. As shown in the computer simulations, the proposed adaptive DFE receiver is robust against the estimation errors and modeling dynamics of the channels. Hence, it is very suitable for receiver design in data transmissions through multipath fading channels encountered in most wireless communication systems.

Performance analysis of an underwater acoustic communications time diversity receiver

One method for introducing time diversity into a decision feedback equalizer (DFE) spatial diversity communications receiver operating in an underwater acoustic environment is presented and analyzed. Time diversity refers to the repetition of transmitted packets and the subsequent batch processing of these packets by an appropriately modified multichannel receiver. To overcome the effects of the time-varying nature of the channel, the modifications made to the spatial diversity-based multichannel DFE (SD-DFE) include appropriate Doppler shift compensation for each received packet and determination of the proper alignment among the time-displaced packets to allow for successful equalization. The proposed time diversity DFE (TD-DFE) receiver is shown to achieve a high rate of packet success under a variety of channel conditions. More significantly, the TD-DFE algorithm is able to equalize packets when a comparable SD-DFE might fail. The packet-to-packet coherence of a series of transmissions is analyzed to provide insight into how the characteristics of the channel affect the performance of the TD-DFE. This analysis illustrates why a time diversity-based equalization approach can be more robust for the underwater acoustic channel as compared to a standard TD-DFE algorithm at the possible expense of reducing throughput.

Performance of a dual-rate DS-CDMA-DFE in an overlaid cellular system

The performance of a direct-sequence code-division multiple-access (DS-CDMA) system in an overlaid cell environment using a decision feedback equalizer (DFE) receiver is presented. It is shown that a DFE receiver can separate the desired signal from several interfering signals without any loss in the overall capacity. The results indicate that DS-CDMA with a DFE receiver can be used to integrate dual-rate services without adversely affecting the system capacity. The overall system capacity is shown to be approximately equal to half the spreading gain and is unaffected when interferers at different data rates are present. The proposed scheme needs only average power control and is not found to be sensitive to power control errors of /spl plusmn/2 dB.