Current-integrating summer for DFE receiver with low common mode variation

Abstract

This paper presents the design of current integrating based decision feedback equalizer (DFE) receiver. The proposed DFE incorporates a folded topology of current integrating summer which has reduced common mode voltage drop and variation at the summing nodes compared to existing topologies. The DFE uses a half-rate, soft decision architecture to alleviate the timing constraint of first feedback tap. Further, direct feedback architecture and reduced supply voltage are employed to reduce the power consumption. The DFE receiver has been implemented in 65 nm CMOS technology and operates at a data rate of 8 Gb/s over an 18.5 inch FR4 channel which has a loss of about 12.4 dB at 4 GHz frequency. It draws a current of 3.89 mA from a 0.9 V supply consuming a power of 3.5 mW.