Decimal Operations Research Articles

Self-Supervised Deep Blind Video Super-Resolution.

Existing deep learning-based video super-resolution (SR) methods usually depend on the supervised learning approach, where the training data is usually generated by the blurring operation with known or predefined kernels (e.g., Bicubic kernel) followed by a decimation operation. However, this does not hold for real applications as the degradation process is complex and cannot be approximated by these idea cases well. Moreover, obtaining high-resolution (HR) videos and the corresponding low-resolution (LR) ones in real-world scenarios is difficult. To overcome these problems, we propose a self-supervised learning method to solve the blind video SR problem, which simultaneously estimates blur kernels and HR videos from the LR videos. As directly using LR videos as supervision usually leads to trivial solutions, we develop a simple and effective method to generate auxiliary paired data from original LR videos according to the image formation of video SR, so that the networks can be better constrained by the generated paired data for both blur kernel estimation and latent HR video restoration. In addition, we introduce an optical flow estimation module to exploit the information from adjacent frames for HR video restoration. Experiments show that our method performs favorably against state-of-the-art ones on benchmarks and real-world videos.

Approaching the Ideal Linearity in Epitaxial Crystalline-Type Memristor by Controlling Filament Growth.

Brain-inspired neuromorphic computing has attracted widespread attention owing to its ability to perform parallel and energy-efficient computation. However, the synaptic weight of amorphous/polycrystalline oxide based memristor usually exhibits large nonlinear behavior with high asymmetry, which aggravates the complexity of peripheral circuit system. Controllable growth of conductive filaments is highly demanded for achieving the highly linear conductance modulation. However, the stochastic behavior of the filament growth in commonly used amorphous/polycrystalline oxide memristor makes it very challenging. Here, the epitaxially grown Hf0.5Zr0.5O2-based memristor with the linearity and symmetry approaching ideal case is reported. A layer of Cu nanoparticles is inserted into epitaxially grown Hf0.5Zr0.5O2 film to form the grain boundaries due to the breaking of the epitaxial growth. By combining with the local electric field enhancement, the growth of filament is confined in the grain boundaries due to the fact that the diffusion of oxygen vacancy in crystalline lattice is more difficult than that in the grain boundaries. Furthermore, the decimal operation and high-accuracy neural network are demonstrated by utilizing the highly linear and multi-level conductance modulation capacity. This method opens an avenue to control the filament growth for the application of resistance random access memory (RRAM) and neuromorphic computing.

Memristors Constructed by CsPbIBr2 Inorganic Halide Perovskite for Artificial Synapse and Logic Operation

Neuromorphic devices are one of the promising electronic devices that are implementing artificial neural networks and substituting for traditional semiconductor devices in recent years. Inorganic halide perovskite (IMHP) is considered as an advantageous material to constitute neuromorphic components. Herein, the CsPbIBr2 memristor displays superior resistive‐switching properties under various temperature and storage periods. In addition, synaptic plasticity, including paired pulse facilitation and spiking timing‐dependent plasticity, is observed for CsPbIBr2 device, whose resistance manipulation is also established in both DC and pulse modes. Moreover, the decimal operation function of numbers by applying pulse stimulation to the device to regulate the device conductance is realized. This work demonstrates the feasibility of IMHP in neuromorphic devices, accelerating the application of neuromorphic computing.

Efficient Sigma-Delta Sensor Array Beamforming.

Nowadays, sensors with built-in sigma-delta modulators (ΣΔMs) are widely used in consumer, industrial, automotive, and medical applications, as they have become a cost-effective and convenient way to deliver data to digital processors. This is the case for micro-electro-mechanical system (MEMS), digital microphones that convert analog audio to a pulse-density modulated (PDM) bitstream. However, as the ΣΔMs output a PDM signal, sensors require either built-in or external high-order decimation filters to demodulate the PDM signal to a baseband multi-bit pulse-code modulated (PCM) signal. Because of this extra circuit requirement, the implementation of sensor array algorithms, such as beamforming in embedded systems (where the processing resources are critical) or in very large-scale integration (VLSI) circuits (where the power and area are crucial) becomes especially expensive as a large number of parallel decimation filters are required. This article proposes a novel architecture for beamforming algorithm implementation that fuses delay and decimation operations based on maximally flat (MAXFLAT) filters to make array processing more affordable. As proof of concept, we present an implementation example of a delay-and-sum (DAS) beamformer at given spatial and frequency requirements using this novel approach. Under these specifications, the proposed architecture requires 52% lower storage resources and 19% lower computational resources than the most efficient state-of-the-art architecture.

Flexible Memristor Constructed by 2D Cadmium Phosphorus Trichalcogenide for Artificial Synapse and Logic Operation (Adv. Funct. Mater. 9/2023)

Transition-Metal Phosphorus Trichalcogenide In article number 2211269, Jiahong Wang, Cong Ye, and co-workers report a flexible memristor fabricated utilizing two-dimensional cadmium phosphorus trichalcogenide nanosheets; the synaptic plasticity, including paired-pulse facilitation and spiking timing-dependent plasticity, are further observed. Owing to the linear conductance modulation capacity, the decimal operation is explored.

Flexible Memristor Constructed by 2D Cadmium Phosphorus Trichalcogenide for Artificial Synapse and Logic Operation

AbstractThe development of advanced microelectronics requires new device architecture and multi‐functionality. Low‐dimensional material is considered as a powerful candidate to construct new devices. In this work, a flexible memristor is fabricated utilizing 2D cadmium phosphorus trichalcogenide nanosheets as the functional layer. The memristor exhibits excellent resistive switching performance under different radius and over 103 bending times. The device mechanism is systematically investigated, and the synaptic plasticity including paired‐pulse facilitation and spiking timing‐dependent plasticity are further observed. Furthermore, based on the linearly conductance modulation capacity of the flexible memristor, the applications on decimal operation are explored, that the addition, subtraction, multiplication, and division of decimal calculation are successfully achieved. These results demonstrate the potential of metal phosphorus trichalcogenide in novel flexible neuromorphic devices, which accelerate the application process of neuromorphic computing.

A Digital Learning Game for Mathematics that Leads to Better Learning Outcomes for Female Students: Further Evidence

Stereotypes about men being better than women at mathematics appear to influence female students’ interest and performance in mathematics. Given the potential motivational benefits of digital learning games, it is possible that games could help to reduce math anxiety, increase self-efficacy, and lead to better learning outcomes for female students. We are exploring this possibility in our work with Decimal Point, a digital learning game that scaffolds practice with decimal operations for 5th and 6th grade students. In several studies with various versions of the game, involving over 800 students across multiple years, we have consistently uncovered a learning advantage for female students with the game. In our most recent investigation of this gender effect, we decided to experiment with a central feature of the game: its use of prompted self-explanation to support student learning. Prior research has suggested that female students might benefit more from self-explanation than male students. In the new study, involving 214 middle school students, we compared three versions of self-explanation in the game – menu-based, scaffolded, and focused – each presenting students with a different type of prompted self-explanation after they solved problems in the game. We found that the focused approach led to more learning across all students than the menu-based approach, a result reported in an earlier paper. In the additional results reported in this paper, we again uncovered the gender effect – female students learned more from the game than male students, regardless of the version of self-explanation – and also found a trend in which female students made fewer self-explanation errors, suggesting they may have been more deliberate and thoughtful in their self-explanations. This self-explanation finding is a possible key to further investigation into how and why we see the gender effect in Decimal Point.

A Novel Decimal Arithmetic Operations By using FPGA Logic Block Architecture

To improve the efficiency of decimal computation functions in Field-Programmable Gate Array (FPGAs) are used by Hardened adder and carry logic. There are many design choices and complexities associated with such hardening, FPGA architectural choices, power consumption. Moreover, those choices have not been studied much and hence i explore a number of possibilities.For avoiding inaccuracy, introduced when converting fragment of numeric to double, these data are processed with decimal computation operation. Most processors only have hardwired double computation units. So, decimal operations are executed with slow software decimal computation functions. For the fast output of decimal operations, devoted tackle units have been proposed and designed in Field Programmable Gate Array.Compared to former architectures, my perpetration results show that the proposed computation operations achieve 15 percent better area and 12% better performance.

Identifying Preservice Teachers’ Concept-based and Procedure-based Error patterns in Multiplying and Dividing Decimals

The purposes of this study are to report current Preservice Teachers’ (PTs) decimal abilities regarding the types of error patterns that they commit and to analyze characteristics of the errors in the problems posed for multiplication and division in decimals. We have determined common concept- and procedure-based errors made by the PTs. 37 PTs in the USA were asked to complete two decimal multiplication problems and two decimal division problems. Results indicated that four major types of error patterns could be detected: Misunderstanding of the place value, misunderstanding of mathematical equivalence, arithmetic errors, and reversing the positions of divisor and dividend. PTs were more likely to have concept- than procedure-based errors. This indicates that PTs may have limited knowledge on the definition of decimals and the meaning of mathematical equivalence, as well as a lack of understanding of place value. Consequently, we believe that the learning of the concept of decimals requires conceptual change. The concept-based errors found intersect with those of students in primary school, so this helps Teacher Education programs in ways that promote PTs’ mathematical understanding of decimal operations on a conceptual basis to prevent their future students from making errors.

Angle-bounded 2D mesh simplification

We describe a method to simplify a 2D triangle mesh through decimation while preserving its quality by means of maintaining a strict lower bound on inner angles. Conformance to boundaries, interfaces, and feature constraints is preserved as well. Multiple options and strategies for the choice of local decimation operators and for the settling of geometric degrees of freedom are proposed and explored. A systematic evaluation leads to a final recommendation for the most beneficial approach. The resulting method enables the efficient generation of more parsimonious meshes than those obtained from existing methods, while exhibiting the same quality in terms of worst element shape, as is relevant, for instance, in finite element analysis and numerical simulation.

Universal Filtered Multicarrier Receiver Complexity Reduction to Orthogonal Frequency Division Multiplexing Receiver

The Universal Filtered Multicarrier (UFMC) waveform technology is one of the promising waveforms for 5G and beyond 5G networks. Owing 2N-point Fast Fourier Transform (FFT) processor at the UFMC receiver, the computational and implementation complexity is two times more than the conventional Orthogonal Frequency Division Multiplexing (OFDM) receiver system. In this paper, we proposed a simplified UFMC receiver structure to reduce computational complexity as well as hardware requirements. The received UFMC symbol simplified exactly to its equivalent after performing 2N-point FFT and decimation operations. In which, the mathematical model of the frequency-domain UFMC signal is rederived after processing through 2N-point FFT and decimator, and the simplified signal is generated with an N-point FFT. Accordingly, the 2N-point FFT processor and decimator are replaced with a single N-point FFT processor. This approach reduces the 50% computational complexity at the FFT processor level hence the hardware and processing time. The computational complexity of the proposed receiver model is approximately equivalent to the OFDM receiver. Additionally, analyzed the mathematical model for the simplified UFMC receiver and the comparative performance of the UFMC system with the conventional model.

Devising methods to synthesize discrete complex signals with required properties for application in modern information and communication systems

Information and communication systems (ICSs) must comply with increasingly stringent requirements to ensure the reliability and speed of information transmission, noise immunity, information security. This paper reports the methods to synthesize discrete complex cryptographic signals, underlying the construction of which are random (pseudo-random) processes; the methods for synthesizing characteristic discrete complex signals whose construction is based on using the nature of the multiplicative group of a finite field; the results of studying the properties of the specified signal systems. It is shown that the methods built provide a higher synthesis performance than known methods and make it possible to algorithmize the synthesis processes for the construction of software and hardware devices to form such signals. The win in the time when synthesizing nonlinear signals in finite fields using the devised method is, compared to the known method, for the period of 9,972 elements is 1,039.6 times. The proposed method for synthesizing the entire system of such signals, based on decimation operation, outperforms the known method of difference sets in performance. Thus, for a signal period of 2,380 elements, the win in time exceeds 28 times. It has also been shown that the application of such systems of complex signals could improve the efficiency indicators of modern ICSs. Thus, the imitation resistance of the system, when using complex discrete cryptographic signals with a signal period of 1,023 elements, is four orders of magnitude higher than when applying the linear signal classes (for example, M-sequences). For a signal period of 1,023 elements, the win (in terms of structural secrecy) when using the signal systems reported in this work exceeds 300 times at a period of 8,192, compared to the signals of the linear form (M-sequences)

Decimal Multiplication in FPGA with a Novel Decimal Adder/Subtractor

Financial and commercial data are mostly represented in decimal format. To avoid errors introduced when converting some decimal fractions to binary, these data are processed with decimal arithmetic. Most processors only have hardwired binary arithmetic units. So, decimal operations are executed with slow software-based decimal arithmetic functions. For the fast execution of decimal operations, dedicated hardware units have been proposed and designed in FPGA. Decimal multiplication is found in most decimal-based applications and so its optimized design is very important for fast execution. In this paper two new parallel decimal multipliers in FPGA are proposed. These are based on a new decimal adder/subtractor also proposed in this paper. The new decimal multipliers improve state-of-the-art parallel decimal multipliers. Compared to previous architectures, implementation results show that the proposed multipliers achieve 26% better area and 12% better performance. Also, the new decimal multipliers reduce the area and performance gap to binary multipliers and are smaller for 32 digit operands.

Preservice Teachers' Understanding of Decimals using Standard Algorithm and Alternative Strategies

The purpose of this study is to explore preservice teachers’ (PTs’) ability to implement multiple strategies using standard algorithms and alternative strategies and to investigate their conceptual knowledge of decimal operations. There were 37 PTs who participated in this study, all of whom attended a mathematics course in the K-8 Teacher Education Program at a mid-western university. These participants were asked to solve the Decimal Knowledge Test (DKT) in multiple ways. A qualitative approach was used to analyze PTs’ responses to the problems on the DKT. The results indicated that using standard algorithms, PTs demonstrated higher ability in solving decimal addition, subtraction, and multiplication involving a whole number. Alternative strategies posed difficulties in solving decimal multiplication problems involving two decimals, and division problems. Similarly, when examining operations, showing smooth or difficult translations between the representations, PTs found it difficult to translate representational modes in operations with multiplication involving two decimals, two division problems. The same results were seen when examining PTs’ conceptual understanding based on the Lesh Translation Model. The results provide teacher education programs with opportunities to create various instructional approaches involving translations among multiple representations in mathematics methods and content courses.

Decimation and interleaving operations in one-sided symbolic dynamics

This paper studies subsets of one-sided shift spaces on a finite alphabet. Such subsets arise in symbolic dynamics, in fractal constructions, and in number theory. We study a family of decimation operations, which extract subsequences of symbol sequences in infinite arithmetic progressions, and show these operations are closed under composition. We also study a family of n-ary interleaving operations, one for each n≥1. Given subsets X0,X1,...,Xn−1 of such a shift space, the n-ary interleaving operation produces a set whose elements combine individual elements xi, one from each Xi, by interleaving their symbol sequences in arithmetic progressions (modn). We determine algebraic relations between decimation and interleaving operations and the shift map. We study set-theoretic n-fold closure operations X↦X[n], which interleave decimations of X of modulus level n. A set is n-factorizable if X=X[n]. The n-fold interleaving operations are closed under composition and are idempotent. To each X we assign the set N(X) of all values n≥1 for which X=X[n]. We characterize the possible sets N(X) as nonempty sets of positive integers that form a distributive lattice under the divisibility partial order and are downward closed under divisibility. We show that all sets of this type occur. We introduce a class of weakly shift-stable sets and show that this class is closed under all decimation, interleaving, and shift operations. We study two notions of entropy for subsets of the full one-sided shift and show that they coincide for weakly shift-stable X, but can be different in general. We give a formula for entropy of interleavings of weakly shift-stable sets in terms of individual entropies.

Methods of synthesis and formation of a system of nonlinear discrete signals for modern information and communication systems

The paper presents the results of solving the urgent problem of improving the performance indicators of information and communication systems (ICS), in particular, information security, noise immunity, secrecy, the speed of formation and processing of information. The use of the distributed spectrum technology (broadband noise-like signals) is a promising direction for ensuring the security of information resources. The methods used for data formation and processing, as well as the classes of broadband signals used as physical data carriers, do not allow providing the necessary (especially for critical infrastructure facilities) indicators of information security and noise immunity. In this case, as discrete sequences (DS) that expand the spectrum (manipulate the carrier frequency), should be used DS based on nonlinear construction rules and having improved correlation, ensemble and structural properties. Methods for the synthesis and formation of nonlinear discrete complex signals, namely, the so-called cryptographic signals, are proposed. The first method, presented in the article, uses random (pseudo-random) processes. Another method is based on the implementation of the operation of decimation of the original discrete sequence of symbols obtained from the results of the implementation of the first method; it provides the synthesis of an ensemble of signals for a certain signal duration. Analytical expressions are obtained for determining the synthesis time of an ensemble of signals using the proposed methods. It is shown that the speed of the signal generation method based on the decimation operation for a certain signal duration is more than three orders of magnitude higher than the speed of the method based on the random (pseudo-random) processes used. At the same time, based on the carried out computer simulation, it is shown that the signals obtained using the proposed methods have identical correlation, ensemble, and structural properties.

Mathematical Model for Approximation the Efficiency of Parallel Computing on Single Board Cluster with Least-squares Approximation

This research aims to study the relationship between parallel processing efficiency and several nodes on a single board cluster using a mathematical model, approximating least squares. This research tested on the Raspberry Pi single-board in the form of a high-performance computing system. It divided the tasks that need to be processed in each particular part and sent it to each unit to process simultaneously via the MPI (Messaging Passing Interface). This process is the standard division of work with communication between processors in the form of messages on the cluster system. It consists of eight nodes of Raspberry Pi. It measures the instruction set's ability to perform decimal operations per second or Floating-point Operation Per Second (FLOPS) with High-Performance Linpack Benchmarks (HPL). As a result, the efficiency of the ability to process instruction set in decimal per second increases the performance continuously when increasing the number of the node on the cluster. Which corresponds to the mathematical model obtained f(x) = 1.0684x^(0.8256).It shows a relationship between parallel processing performance values and the number of nodes on the cluster and can be estimated with the mathematical model above.

Conhecimento especializado nos currículos de matemática na concepção dos professores

Apresentamos neste artigo um recorte da tese de doutorado cujo problema é: Quais são os conhecimentos matemáticos, relativos a conceitos, procedimentos e atitudes, considerados fundamentais para construção de uma Base Nacional Comum Curricular (BNCC) na concepção dos professores de Matemática da 27ª Coordenadoria Regional de Educação (CRE) do estado do Rio Grande do Sul? A pesquisa tem como objetivo investigar a concepção dos professores de Matemática quanto aos conhecimentos matemáticos, considerados fundamentais para construção de uma BNCC. A metodologia utilizada, nessa investigação é de base qualitativa. Os dados obtidos são oriundos de entrevistas de pesquisa aplicados aos professores de Matemática da rede municipal de Canoas/RS, realizadas com uma amostra dos participantes da pesquisa. Como resultado da pesquisa destaca-se a constatação dos professores de Matemática, apontando que nas escolas investigadas estão ocorrendo reuniões e discussões sobre a implementação da BNCC, sendo que em 2020 haverá a implantação definitiva da base em todas as escolas que compõem o território nacional brasileiro, sendo públicas ou particulares. Os principais temas considerados fundamentais para os professores foram: Números Naturais: Sistema de numeração decimal, operações, Números Inteiros, potenciação e radiciação, Números Reais, propriedades da igualdade, equações polinomiais do 1º grau, funções, expressões algébricas, semelhança de triângulos, volume de prismas e cilindros e o princípio multiplicativo da contagem.

Face Identification Using HAAR Wavelet Transform

Face identification is the process of matching one or more people by analyzing and comparing the patterns of their faces. Algorithms for face identification typically extract facial features and compare them to a database to find the best match. The Haar wavelet transform has been mainly used for image processing and pattern identification due to its low computing requirements and quality to conserve and to compact the energy of a signal. In discrete wavelet transform, an image signal can be analyzed by passing it through an analysis filter bank followed by a decimation operation. Face identification has been performed in terms of correlation coefficient, Euclidean distance and sum of absolute difference.

Face Identification Using HAAR Wavelet Transform

Face identification is the process of matching one or more people by analyzing and comparing the patterns of their faces. Algorithms for face identification typically extract facial features and compare them to a database to find the best match. The Haar wavelet transform has been mainly used for image processing and pattern identification due to its low computing requirements and quality to conserve and to compact the energy of a signal. In discrete wavelet transform, an image signal can be analyzed by passing it through an analysis filter bank followed by a decimation operation. Face identification has been performed in terms of correlation coefficient, Euclidean distance and sum of absolute difference.