A Novel Decimal Arithmetic Operations By using FPGA Logic Block Architecture

Abstract

To improve the efficiency of decimal computation functions in Field-Programmable Gate Array (FPGAs) are used by Hardened adder and carry logic. There are many design choices and complexities associated with such hardening, FPGA architectural choices, power consumption. Moreover, those choices have not been studied much and hence i explore a number of possibilities.For avoiding inaccuracy, introduced when converting fragment of numeric to double, these data are processed with decimal computation operation. Most processors only have hardwired double computation units. So, decimal operations are executed with slow software decimal computation functions. For the fast output of decimal operations, devoted tackle units have been proposed and designed in Field Programmable Gate Array.Compared to former architectures, my perpetration results show that the proposed computation operations achieve 15 percent better area and 12% better performance.