Decimal Matrix Code Research Articles

Proficient matrix codes for error detection and correctionin 8-port network on chip routers

This paper verifies the applicability of the proposed code to dynamic Network on Chips that have variable faulty blocks with runtime suggesting an online error detection mechanism with adaptive routing algorithm that bypasses faulty components dynamically and the router architecture uses additional diagonal state indications for the reliable network on chip (NoC) operation. In NoC, the permanently faulty routers are disconnected to enable high runtime throughput as data packets are not lost due to self-loopback mechanism. The proposed proficient matrix codes use the capabilities of decimal matrix code technique with minimum check bits for maximum error correction capability. The proposed code is compared with existing codes such as decimal matrix codes, modified decimal matrix codes and parity matrix codes. The codes are developed in verilog hardware description language and simulated in the Xilinx ISE 14.5 tool. This proficient matrix code proves to be efficient for multiple adjacent error detection and correction with trade off in delay. Also 65% code rate is achieved with 22.73% less redundant bits that occupy less area by atleast 11.78%. The codes when used for increased data sizes like 8, 16, 32, and 64 bits, the power delay product decreased by atleast 1.74%.

DESIGN AND DEVELOPMENT OF ENHANCED MEMORY RELIABILITY AGAINST MULTIPLE CELL UPSETS USING DMC

Transient multiple cell upsets (MCUs) are beginning to seriously affect the reliability of memories when they are exposed to radiation settings. More complex error correction codes (ECCs) are often used to protect memory and prevent data corruption caused by MCUs; nevertheless, their primary drawback is an increase in delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The two error correction codes and the fact that not all situations lead to an improvement in mistake correction skills are the main issues. This work proposes a revolutionary decimal matrix code (DMC) based on the divide-symbol to provide better memory reliability with minimal delay overhead. The proposed DMC uses the decimal algorithm to provide the maximum amount of error detection capability. Furthermore, to minimize the area overhead of extra circuits without interfering with the encoding and decoding processes, it is advised to implement the encoder-reuse method (ERT)

Potent Error Detection and Correction Making Use of Decimal Matrix Code for Reminiscence Reliability

Transient multichip(MCU) that's upset fitting further outstanding influences with tremendous outcome on memory dependability. It is principal to defend reminiscence cells using security codes, for this particular rationale just a few mistake correction codes (ECCs) are employed, however the situation is they could need difficult constitution(encoder and decode). Decimal matrix code (DMC) can be used to scale back the area a nd prolong overhead. Hamming codes had been proposed for memory protection. The drawback that's important that mistake amendment potential potentially no longer more fine in each occasions. DMC headquartered on divide-symbol method with encoder reuse method (ERT) used for scale back area overhead circuits which are extra.

Lookup Table Algorithm for Error Correction in Color Images

Error correction and error detection techniques are often used in wireless transmission systems. A color image of type BMP is considered as an application of developed lookup table algorithms to detect and correct errors in these images. Decimal Matrix Code (DMC) and Hamming code (HC) techniques were integrated to compose Hybrid Matrix Code (HMC) to maximize the error detection and correction. The results obtained from HMC still have some error not corrected because the redundant bits added by Hamming codes to the data are considered inadequate, and it is suitable when the error rate is low for detection and correction processes. Besides, a Hamming code could not detect large burst error period, in addition, the have same values sometimes which lead to not detect the error and consequently increase the error ratio. The proposed algorithm LUT_CORR is presented to detect and correct errors in color images over noisy channels, the proposed algorithm depends on the parallel Cyclic Redundancy Code (CRC) method that's based on two algorithms: Sarwate and slicing By N algorithms. The LUT-CORR and the aforementioned algorithms were merged to correct errors in color images, the output results correct the corrupted images with a 100 % ratio almost. The above high correction ratio due to some unique values that the LUT-CORR algorithm have. The HMC and the proposed algorithm applied to different BMP images, the obtained results from LUT-CORR are compared to HMC for both Mean Square Error (MSE) and correction ratio. The outcome from the proposed algorithm shows a good performance and has a high correction ratio to retrieve the source BMP image.

Detection and Correction of Multiple Upsets in Memories Using Modified Decimal Matrix Code

Detection and Correction of Multiple Upsets in Memories Using Modified Decimal Matrix Code

Reliability of Memory Storage System UsingDecimal Matrix Code and Meta-Cure

Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used. The soft error rate in memory cells Multiple Cell Upset (MCU) are rapidly increasing. MCU have become a serious reliability issue in the memory. A novel Decimal Matrix Code (DMC) based on divide- symbol is proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. The Encoder-Reuse Technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be a part of the decoder. The increasing density of NAND flash memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multibiterrors.Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data, such as file system metadata. Redundant pairs are formed at run time and distributed to different physical pages to protect against failure.

English

Protection codes are necessary to shield memory cells, to maintain good quality level of reliability. But, we don’t find any optimized error detection and correction methods. Therefore, in this paper, we present a high performance Decimal Matrix Code to assure the reliability of memory. This protection code utilizes decimal procedure to detect errors, so that more errors were detected and corrected up to 32. Transient multiple cell upsets (MCUs) are major problems in the reliability of memories exposed to radiation environment. To prevent cell upsets from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but they would require higher delay so an efficient ERT (encoder-reuse technique) is proposed to reduce the area overhead of extra circuits, it utilize DMC encoder itself to be part of the decoder.

English

The proposed security code utilizes decimal method to detect errors, so that more errors were detected and corrected. At the present days to maintain good level of reliability, it is required to protect memory cells using protection codes, for this purpose, various error detection and correction methods are being used. In the paper 64-bit Decimal Matrix Code was proposed to assure the dependability of memory. Here to detect and correct up to 50% errors. The results showed that the proposed scheme has a protection level against large MCUs in memory. To avoid MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would need higher delay overhead. Previously, matrix codes (MCs) based on Hamming codes include been proposed for memory safety. The main problem is that they are double error correction codes and the error correction capabilities are not enhanced in each case. Transient multiple cell upsets (MCUs) are appropriate major problems in the reliability of memories exposed to energy environment. In the new method we are implement 64-bit decimal matrix for error correction in memories. In the new method to increase the error correction rate compared to the 32-bit decimal matrix code. Moreover, the ERT (encoder-reuse technique) is proposed to decrease the area transparency of extra circuits exclusive of disturbing the total encoding and decoding processes. ERT (encoder re use technique) use DMC encoder itself to be part of in the decoder.

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code

Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not improved in all cases. In this paper, novel decimal matrix code (DMC) based on divide-symbol is proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. Moreover, the encoder-reuse technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The proposed DMC is compared to well-known codes such as the existing Hamming, MCs, and punctured difference set (PDS) codes. The obtained results show that the mean time to failure (MTTF) of the proposed scheme is 452.9%, 154.6%, and 122.6% of Hamming, MC, and PDS, respectively. At the same time, the delay overhead of the proposed scheme is 73.1%, 69.0%, and 26.2% of Hamming, MC, and PDS, respectively. The only drawback to the proposed scheme is that it requires more redundant bits for memory protection.