Deadlock-free Routing Algorithm Research Articles

Graph based routing algorithm for torus topology and its evaluation for the Angara interconnect

Several approaches and techniques exist to resolve load balancing problem in general and torus topology networks. Graph methods are natural ways to perform balancing of routing paths. A routing balancing algorithm must operate within the constraints of the underlying network architecture that limits several parameters, such as the number of logical paths in the network. In this paper, we consider a torus topology that is one of the common topologies that are used in high performance computing systems. We introduce a routing graph that corresponds to a interconnect topology, abstracts interconnect routing rules, providing one-to-one correspondence of network routes and graph paths. We propose a deadlock-free routing algorithm based on a fast single-source shortest path algorithm in a routing graph for the deterministic routing of a torus topology interconnect with a single virtual channel. The proposed algorithm is a tradeoff between two existing routing algorithms, also the algorithm is optimized for multidimensional torus topology and can be applied to any torus topology HPC system. We present a complete description of a routing graph that abstracts the Angara interconnect with 4D torus topology. We evaluated the proposed routing algorithm and benchmarked the maximum performance improvement of 71% for the Alltoall pattern for torus topology systems up to 432 nodes on the Angara interconnect simulator. The performance improvement of more than 5% was obtained for the NPB FT and IS application kernels on a 32-node supercomputer.

Ring-Split: Deadlock-Free Routing Algorithm for Circulant Networks-on-Chip.

This article considers the usage of circulant topologies as a promising deadlock-free topology for networks-on-chip (NoCs). A new high-level model, Newxim, for the exploration of NoCs with any topology is presented. Two methods for solving the problem of cyclic dependencies in circulant topologies, which limit their applications for NoCs due to the increased possibility of deadlocks, are proposed. The first method of dealing with deadlocks is universal and applicable to any topology; it is based on the idea of bypassing blocked sections of the network on an acyclic subnetwork. The second method-Ring-Split-takes into account the features of circulant topologies. The results of high-level modeling and comparison of the peak throughput of NoCs for circulant and mesh topologies using deadlock-free routing algorithms are presented. It was shown that a new approach for routing in circulants (compared to mesh topology) shows up to 59% better network throughput with a uniform distribution of network load.

Deadlock-Freedom in Computational Neuroscience Simulators

This article presents deadlock-free routing algorithms for interconnection networks of computational neuroscience simulators.

Leveraging InfiniBand controller to configure deadlock-free routing engines for Dragonflies

The Dragonfly topology is currently one of the most popular network topologies in high-performance parallel systems. The interconnection networks of many of these systems are built from components based on the InfiniBand specification. However, due to some constraints in this specification, the available versions of the InfiniBand network controller (OpenSM) do not include routing engines based on some popular deadlock-free routing algorithms proposed theoretically for Dragonflies, such as the one proposed by Kim and Dally based on Virtual-Channel shifting. In this paper we propose a straightforward method to integrate this routing algorithm in OpenSM as a routing engine, explaining in detail the configuration required to support it. We also provide experiment results, obtained both from a real InfiniBand-based cluster and from simulation, to validate the new routing engine and to compare its performance and requirements against other routing engines currently available in OpenSM.

Decreasing latency considering power consumption issue in silicon interposer-based network-on-chip

Stacking technology is an approach to improve scalability of 2D network-on-chip systems. 3D stacking technology places multiple chips vertically, while silicon chips are stacked side-by-side on a silicon interposer layer in the 2.5D stacking technology. 2.5D stacking can solve many of the 3D stacking difficulties such as thermal problem. The cores in the processing element (PE) layer must have the ability to connect together. Moreover, the connection between the processing cores and the other chips is a critical issue that should be concerned. The memory chip is one of the most important chips, integrated with the many-core chip. The network-on-chip can be extended to the interposer layer to increase the usability of the interposer layer. It is essential to have an efficient topology and deadlock-free routing algorithm to handle operations effectively and decrease delay and power consumption. In this paper, a new topology called “Balanced Mesh” and a deadlock-free routing algorithm is recommended that balances fairly the connection between different Mesh-based segments of a network. Many of interposer network topologies such as ButterDonut increase the degree of intermediate routers in the interposer layer or nodes related to other chips. Many of them cannot be easily used in the PE layer to have a uniform system. The proposed topology can be simply applied to both of many-core layer and the interposer layer to decrease delay and power consumption without any change in the degree of nodes and has lesser number of links. Our proposed topology is compared with some other topologies such as concentrated Mesh(CMesh) and ButterDount. Simulation results show that our proposed topology can improve the system efficiency with lesser number of links. Using our proposed topology in both layers achieves 13% improvement in network latency compared with using Mesh in the PE layer and ButterDonut in the interposer layer. Also, it achieves 12% improvement in power consumption.

A load-balanced congestion-aware routing algorithm based on time interval in wireless network-on-chip

Network-on-chip (NoC) has been introduced to increase the performance of chip multiprocessors (CMPs) and execute parallel programs. Although NoC is known as a modular and scalable infrastructure for interconnections, there are still some challenges with conventional NoC such as high latency and power consumption due to the communication among long-distance (LD) cores. In this regard, wireless network-on-chip (WiNoC) is a potential solution that can provide high bandwidth and low latency by means of the unique features of wireless interconnects. However, wireless routers (WRs) are prone to congestion in WiNoC due to the limited number of wireless channels on a chip and shared use of these channels by all processing elements (PEs). In this study, a load-balanced time-based congestion-aware (LTCA) routing algorithm is proposed to eliminate the congestion of WRs and distribute the traffic load on the wired and wireless networks in a balanced way. LTCA is a deadlock-free routing algorithm in which only a limited number of packets are allowed to use wireless channels. The required time for transmitting the selected packets through wireless links is measured with regard to the bandwidth of the wireless channels and traffic load. Simulation results on synthetic traffic patterns and real-world 3-tuple traffic patterns indicated a considerable improvement in latency, throughput, wired and wireless link utilization and packet loss probability.

Scalable Deadlock-Free Deterministic Minimal-Path Routing Engine for InfiniBand-Based Dragonfly Networks

Dragonfly topologies are gathering great interest nowadays as one of the most promising interconnect options for High-Performance Computing (HPC) systems. However, Dragonflies contain physical cycles that may lead to traffic deadlocks unless the routing algorithm prevents them properly. In general, existing deadlock-free routing algorithms, either deterministic or adaptive, proposed for Dragonflies, use Virtual Channels (VCs) to prevent cyclic dependencies. However, these topology-aware algorithms are difficult to implement, or even unfeasible, in systems based on the InfiniBand (IB) architecture, which is nowadays the most widely used network technology in HPC systems. This is due to some limitations in the IB specification, specifically regarding the way Virtual Lanes (VLs), which are considered as similar to VCs, can be assigned to traffic flows. Indeed, none of the routing engines currently available in the official releases of the IB control software has been specifically proposed for Dragonflies. In this paper, we present a new deterministic, minimal-path routing for Dragonfly that prevents deadlocks using VLs according to the IB specification, so that it can be straightforwardly implemented in IB-based networks. We have called this proposal D3R (Deterministic Deadlock-free Dragonfly Routing). Specifically, D3R maps each route to a single, specific VL depending on the destination group, and according to a specific order, so that cyclic dependencies (so deadlocks) are prevented. D3R is scalable as it requires only 2 VLs to prevent deadlocks regardless of network size, i.e., fewer VLs than the required by the deadlock-free routing engines available in IB that are suitable for Dragonflies. Alternatively, D3R achieves higher throughput if an additional VL is used to reduce internal contention in the Dragonfly groups. We have implemented D3R as a new routing engine in OpenSM, the control software including the subnet manager in IB. We have evaluated D3R by means of simulation and by experiments performed in a real IB-based cluster, the results showing that, in general, D3R outperforms other routing engines.

A deadlock-free routing algorithm for irregular 3D network-on-chips with wireless links

In recent years, the idea of wireless three-dimensional network-on-chips (3D NoCs) was promoted in order to design many-core chips with greater performance and lower energy consumption. This technology is the combination of different dies that are stacked on each other. Therefore, it is necessary to propose a suitable routing mechanism for irregular wireless 3D NoCs that can support the agnostic topologies. In this paper, we propose a deadlock-free routing algorithm for wireless 3D NoCs, called Floyd-base Inter-chip Traffic distribution (FIT), which is based on Floyd routing algorithm. In FIT algorithm, the number of hops is reduced compared to the already established deterministic algorithms; moreover, the traffic distribution is improved. Evaluation results show that our proposed routing algorithm significantly improves the performance and throughput by reducing the energy consumption, the average hop count and the communication latency.

EbDa

Freedom from deadlock is one of the most important issues when designing routing algorithms in on-chip/off-chip networks. Many works have been developed upon Dally's theory proving that a network is deadlock-free if there is no cyclic dependency on the channel dependency graph. However, finding such acyclic graph has been very challenging, which limits Dally's theory to networks with a low number of channels. In this paper, we introduce three theorems that directly lead to routing algorithms with an acyclic channel dependency graph. We also propose the partitioning methodology, enabling a design to reach the maximum adaptiveness for the n-dimensional mesh and k-ary n-cube topologies with any given number of channels. In addition, deadlock-free routing algorithms can be derived ranging from maximally fully adaptive routing down to deterministic routing. The proposed theorems can drastically remove the difficulties of designing deadlock-free routing algorithms.

An Optimum Value of Dynamic Communication Performance for Midimew Connected Mesh Network

A Midimew connected Mesh Network (MMN) is a proposed hierarchical interconnection network in which numerous basic modules are interconnected in a hierarchical fashion to construct a massively parallel computer. Here, the basic module is the first level of the network which is connected by mesh network while higher level network is connected by a midimew network. In this study, we have evaluated a dynamic communication performance of a variety of MMN using the TOPAZ simulator using a deadlock free routing algorithm with uniform traffic patterns, whereby the dimension order routing and virtual cut-through flow control are used. It is found that the saturation throughput of the Virtual MMN (VMMN) is higher than that of Horizontal MMN (HMMN), Symmetric MMN (SMMN), and Tori connected mESH network (TESH).

DRTL: A heat-balanced deadlock-free routing algorithm for 3D topology network-on-chip

Heat balance is of critical importance on the design of network-on-chip (NoC). In a 3D topology NoC, routing algorithm should take considerations of each layer's peak temperature and traffic to prolong chip's service life. In this paper, we propose a heat-balanced, deadlock-free routing algorithm named Direct Ratio Transport Layer (DRTL). DRTL distributes and arranges traffics according to the source layer and destination layer in order to achieve heat balance in the chip. In this algorithm, if a transition layer is needed, the probability of choosing a layer as the transition layer is inversely proportional to the distance between this layer and the heat sink. Simulation results showed that, compared with Traffic Aware Downward Routing (TADR), congestion is alleviated and the chip achieves good network performance when DRTL is used. Moreover, DRTL gets almost the same network performance as Transport Layer Assisted Routing (TLAR) does while the chip temperature can be lowered by 2K.

REDELF

3D integrated circuits (3D ICs) using through-silicon vias (TSVs) allow to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D network-on-chip (NoC). However, partial vertical connection in 3D NoCs seems unavoidable because of the large overhead of TSV itself (e.g., large footprint, low fabrication yield, additional fabrication processes) as well as the heterogeneity in dimension. This article proposes an energy-efficient deadlock-free routing algorithm for 3D mesh topologies where vertical connections partially exist. By introducing some rules for selecting elevators (i.e., vertical links between dies), the routing algorithm can eliminate the dedicated virtual channel requirement. In this article, the rules themselves as well as the proof of deadlock freedom are given. By eliminating the virtual channels for deadlock avoidance, the proposed routing algorithm reduces the energy consumption by 38.9% compared to a conventional routing algorithm. When the virtual channel is used for reducing the head-of-line blocking, the proposed routing algorithm increases performance by up to 23.1% and 6.9% on average.

Increasing Interconnection Network Throughput with Virtual Channels

Interconnection networks form the backbone of scalable computer systems, including high-performance computers and datacenters. High-performance networks must provide high throughput and bandwidth while delivering messages with minimal latency. As processors that connect to the network inject more messages, the network load rises and can cause two potential deleterious conditions: network deadlock—where messages are blocked in the network and cannot progress—and an exponential increase in end-to-end latency, as messages must wait in the network for prior messages to be delivered. The network architect’s job is to deliver high bandwidth and low latency for the largest network load possible, but with limited cost and power. Before the 1990s, scalable computing systems were typically built with two separate networks to avoid deadlock. These networks were often assigned to “request” and “reply” traffic classes, and messages in separate classes did not interfere as they progressed through the network. The networks had their own individual wires to ensure that reply messages did not get stuck behind request messages. Unfortunately, this approach increases network cost by doubling the number of wires, and can leave links idle as congestion rises. In “Virtual Channel Flow Control” (IEEE Trans. Parallel and Distributed Systems, vol. 3, no. 2, 1992, pp. 194–205), William J. Dally proposed an alternate approach to alleviate deadlock and provide better network performance. Virtual channels include two or more virtualized networks that share the physical wire links and routers, but have their own buffer storage for in-flight messages. In modern interconnection networks, messages are decomposed into flow-control digits (flits) that transit the network like train cars. When a message reaches a congested point, its flits reside in the virtual channel buffers, leaving the links free for messages belonging to other virtual channels. The decoupling of buffering from links in virtual channels enables deadlock-free routing algorithms and the passing of blocked messages in the network, using otherwise idle link resources. With virtual channels, a system doesn’t incur the link cost of multiple networks and can more easily multiplex traffic from different flows over a single set of physical links.

Balancing virtual channel utilization for deadlock-free routing in torus networks

Torus networks have been widely used by modern commercial supercomputers due to low node degree and linear scalability cost. Meanwhile, the ring in each dimension of a torus creates cyclic channel dependencies, which pose challenges to the design of deadlock-free routing and virtual channel allocation schemes. Existing virtual channel allocation schemes such as dateline employ two virtual channels to avoid deadlock in a ring. While the unbalanced utilization of virtual channels caused by these deadlock avoidance schemes brings lots of performance pathologies. This paper focuses on improving deadlock-free routing algorithms in torus by balancing virtual channel utilization. First, we propose BVCU, a novel virtual channel allocation scheme that can balance the utilization of the two virtual channels used to prevent deadlock. The technique is deadlock free and can achieve almost perfect balanced utilization. Second, we propose a balanced dimension-order routing (BDOR) to provide deadlock-free deterministic routing for $$n$$n-D torus by combining BVCU with dimension-order routing. Also, a balanced fully adaptive routing (BFAR) is proposed. These routing algorithms yield higher performance than existing solutions as they achieve a proper balanced utilization of virtual channels. Finally, simulation results show that the proposed methods achieve up to 16 % throughput improvement.

CSquare: A new kilo-core-oriented topology

As the number of cores in a multicore chip increases, the kilo-core processor will be a trend in Network-on-Chip development. For such case, the network topology needs to scale effectively. In this paper, we propose a new scalable topology for kilo-core-oriented processors named CSquare, a cluster-formed structure, in which each cluster is a variation of the butterfly-tree. For each cluster, the routers adopt parallel-level structure to obtain efficient global connections. With the global interconnections between clusters, the topology scale can be extended at a much faster rate than with only one cluster. For such characters, we propose a deadlock-free routing algorithm for CSquare, called GNCA. Compared with 2D-Mesh and Torus, CSquare employs fewer routers and links. The simulation results indicate that CSquare greatly improves the average latency and throughput under various traffic patterns and consumes less power and area.

A Necessary and Sufficient Condition for Deadlock-Free Message Routing in Communication Networks

Deadlocks are an important issue in the design and analysis of communication networks. Wormhole switching is a popular switching technique in direct networks. It refers to a simple flow control system in computer network that is primarily based on fixed links. It also reduces the latency and storage requirements on each node. Deadlock analysis of routing function is a manual and complex task. In the absence of contention, latencies are proportional to the sum of the packet length and the distances to travel. We propose an algorithm to analyze the deadlock in communication networks. The deadlock-free routing algorithm is the first to automatically check a necessary and sufficient condition for deadlock-free routing. Our algorithm performs Effective analysis in this network.

On Uniform Traffic Pattern of Symmetric Midimew Connected Mesh Network

A Symmetric Midimew Mesh connected network (SMMN) is a hierarchical interconnection networks (HIN) that capable to interconnect vast number of nodes that could reach up to millions of nodes in the network. SMMN has multiple basic modules of 2D-mesh networks that are recursively interconnected by Midimew network to create higher-level networks. In this paper, we explain the architectural details of SMMN,we also present the a deadlock-free routing algorithm for SMMN using four virtual channels and evaluate the performance of dynamic communication of SMMN network using proposed routing algorithm under uniform traffic pattern .We also evaluate the performance of dynamic communication of TESH network using topaz simulator. It is shown that the SMMN network has high throughput and low latency, which yield higher performance of dynamic communication compare to other Hierarchical networks.

Design and analysis of a mesh-based wireless network-on-chip

Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long-distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock-free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture.

Unifying on-chip and inter-node switching within the Anton 2 network

The design of network architectures has become increasingly complex as the chips connected by inter-node networkshave emerged as distributed systems in their own right, complete with their own on-chip networks. In Anton 2, a massively parallel special-purpose supercomputer for molecular dynamics simulations, we managed this complexity by reusing the on-chip network as a switch for inter-node traffic. This unified network approach introduces several design challenges. Maintaining fairness within the inter-node network is difficult, as each hop becomes a sequence of many on-chip routing decisions. We addressed this problem with an inverse-weighted arbiter that ensures fairness with low implementation costs. Balancing the load of inter-node traffic across the on-chip network is also critical, and we adopted an optimization approach to design an appropriate routing algorithm. Finally, the on-chip routers carry inter-node traffic, so they must implement inter-node virtual channels to avoid deadlock. In order to keep the routers small and fast, we developed a deadlock-free routing algorithm that reduces the number of virtual channels by one-third relative to previous approaches. The resulting Anton 2 network implementation efficiently utilizes its inter-node channels and provides low messaging latency, while occupying a modest amount of silicon area

Deadlock free routing algorithm for minimizing congestion in a Hamiltonian connected recursive 3D-NoCs

Network on Chip (NoC) has been proposed as a solution for addressing the challenges in System on Chip (SoC) design. Designing a topology and its routing schemes are vital problems in a NoC. One of the major challenges that designers face today in 3D integration is how to route the data packets within a layer and across the layers in a scalable and efficient manner. In any 3D topology, minimizing the amount of data packet transmissions during the routing is still an open problem. Any efficient traditional routing schemes should avoid deadlocks and minimize network congestion from a source node to a destination node.In this paper, we propose a 3D recursive hyper graph Hamiltonian connected network and we propose a deadlock free routing algorithm to minimize congestion in the network. We show that the proposed topology outperforms the topology presented by Dubois et al. (Elevator-First: a Dealock-free distributed routing algorithm for vertically partially connected 3d-Nocs, IEEE Trans. Comput. 62(3) (2013) 609–615) [1] with respect to average network latency. Also, we analysis the delay bound of the switches for the proposed topology and 3D Partially connected Mesh Topology (PMT) and conclude that our topology performs better than 3D PMT.