DRTL: A heat-balanced deadlock-free routing algorithm for 3D topology network-on-chip

Abstract

Heat balance is of critical importance on the design of network-on-chip (NoC). In a 3D topology NoC, routing algorithm should take considerations of each layer's peak temperature and traffic to prolong chip's service life. In this paper, we propose a heat-balanced, deadlock-free routing algorithm named Direct Ratio Transport Layer (DRTL). DRTL distributes and arranges traffics according to the source layer and destination layer in order to achieve heat balance in the chip. In this algorithm, if a transition layer is needed, the probability of choosing a layer as the transition layer is inversely proportional to the distance between this layer and the heat sink. Simulation results showed that, compared with Traffic Aware Downward Routing (TADR), congestion is alleviated and the chip achieves good network performance when DRTL is used. Moreover, DRTL gets almost the same network performance as Transport Layer Assisted Routing (TLAR) does while the chip temperature can be lowered by 2K.